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Dynamic path distribution method and system applicable to network on chip

A dynamic path, on-chip network technology, applied in transmission systems, digital transmission systems, data exchange networks, etc., can solve problems such as reduced communication performance, large data traffic, local link congestion, etc., to optimize routing paths and balance network loads. , the effect of reducing the blocking rate

Active Publication Date: 2011-08-10
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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AI Technical Summary

Problems solved by technology

[0004] a) When the network load is heavy, local link congestion is likely to occur, resulting in the failure of real-time responses to communication requests on some critical paths;
[0005] b) The network load distribution is uneven; in a certain area of ​​the network, the data flow is too large, and the delay of the data packet is unacceptable, and at the same time, the communication nodes in some areas of the network are idle, and the utilization rate of the network link is too low;
[0006] c) When there is a faulty node in the network or some nodes are temporarily disabled, resulting in an increase in the number of congested links, the communication performance will be greatly reduced

Method used

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  • Dynamic path distribution method and system applicable to network on chip
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  • Dynamic path distribution method and system applicable to network on chip

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Embodiment Construction

[0050] Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:

[0051] Such as figure 1 As shown, the dynamic path allocation system can be divided into node sequence recording module, path mapping module, fault management module, communication task management module and path management module according to its realized functions. The functions of each part are as follows:

[0052] (1) The fault management module judges whether there is a shortest path from the source node to the destination node according to the global network status information for different relative positions, and sends the communication task to the communication task management module for two cases: the existence of the shortest path and the absence of the shortest path. deal with.

[0053] (2) The communication task management module sends the communication tasks with the shortest path directly to the node sequence recording module for pa...

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Abstract

The invention discloses a dynamic path distribution method and system applicable to a network on a chip. The method is characterized in that bandwidth occupancy conditions and fault information of each routing unit in the network on chip are collected in real time, and routing paths with communication tasks are regulated dynamically in accordance with network states, so that the routing paths can avoid congestion and fault links. The distribution system comprises a receiving controller, a fault management module, a communication task management module, a node sequential recording module, a path mapping module, a path management module and a sending controller. According to the distribution method and system, the routing paths with the communication tasks can be optimized under the condition that link congestion and permanent faults occur on the network on chip, the network loads can be balanced, the blocking rate of data packets can be reduced, and the performances can be improved under the condition of the link congestion and fault.

Description

technical field [0001] The invention relates to a dynamic path assignment method and system applied to an on-chip network, which is applied to the field of integrated circuits, in particular to the field of on-chip interconnection network design of integrated circuits. Background technique [0002] With the maturity and further development of deep submicron VLSI process technology, the design of SoC (System on Chip) is facing severe problems, which are mainly manifested in three aspects: the synchronization of wiring delay and global clock , Structural issues such as limited address space and inability to support parallel communication of multiple groups of devices, and system expansion issues. In order to solve the problems encountered in SoC design, some European research institutes proposed the concept of NoC (Network on Chip) in 2000. Its core idea is to transplant computer network technology into chip design and divide the system on chip In order to implement multiple ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L45/28
Inventor 周磊吴宁葛芬张颖周芳
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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