Autosynchronous multichannel parallel storage DDS (direct digital synthesis) signal generator

Abstract

The invention discloses an autosynchronous multichannel parallel storage DDS (direct digital synthesis) signal generator. A data clock phase judgment module is added and used for synchronous detection on a data clock obtained after a sampling clock is subjected to m frequency division by each channel DAC, namely, the DAC internal frequency divider of the k path; if certain path (channel) is asynchronous with a reference data clock, the DAC internal frequency divider of the path (channel) is reconfigured and redetected until all channels are synchronous. According to the invention, the data clock phase judgment module is used for synchronous detection of data pulse of all channels and reconfiguring the DAC internal frequency dividers of the asynchronous channels until the channels are synchronous, so that auto synchronization of wave signals output by all channels is realized.

Description

technical field [0001] The invention belongs to the technical field of multi-channel DDS signal generators, and more specifically relates to an automatic synchronous multi-channel parallel storage DDS signal generator. Background technique [0002] The DDS signal generator adopts Direct Digital Synthesis (DDS for short) technology, which has the characteristics of high frequency resolution, fast conversion time, continuous output waveform phase during frequency switching, and the ability to generate arbitrary waveforms. It has become a signal generator of choice. mainstream. [0003] The DDS signal generator is mainly composed of four parts: a clock generator, a phase accumulator, a waveform lookup table, and a digital-to-analog converter (Digital to Analog Converter, DAC). Its structure diagram is as follows figure 1 shown. [0004] The clock generator generates the sampling clock CLK. On each rising edge of the sampling clock, the N-bit phase accumulator performs an acc...

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Problems solved by technology

But on the one hand, this method requires additional hardware overhead. On the other hand, many current high-speed DACs still have data interpolation processing inside the chip, and the interpolation clock is obtained by frequency division of the sampling clock of the DAC chip. In this case In this case, it is impossible to solve the synchronization problem of the channel output by providing the frequency-divided data clock to the DAC chip, resulting in a random phase difference between the output waveforms.

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