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Method for forming semiconductor pattern and semiconductor layer

A semiconductor and pattern technology, applied in the field of electronics, which can solve the problems of heterogeneous integration dislocation defects and inability to improve performance.

Active Publication Date: 2019-08-20
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, heterogeneous integration can lead to dislocation defects due to lattice mismatch-induced strain and may not improve performance

Method used

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  • Method for forming semiconductor pattern and semiconductor layer
  • Method for forming semiconductor pattern and semiconductor layer
  • Method for forming semiconductor pattern and semiconductor layer

Examples

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Embodiment Construction

[0038] Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the disclosure, and thus the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals denote the same elements throughout.

[0039] Example embodiments of the inventive concepts are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. Accordingly, variations from the illustrated shapes as a result, for example, of manufacturing techniques...

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Abstract

The invention provides a method for forming a semi-conductor image and a semi-conductor layer. The method comprises the following steps: an oxide layer is formed on a substrate, a recessed part is formed in the oxide layer and the substrate, and a semi-conductor image that grows in an epitaxial manner is formed in the recessed part; the semi-conductor image contacts with a part, positioned between the oxide layer and the substrate, of a side wall; the upper surface of a gap in the recessed part in the substrate can be limited.

Description

technical field [0001] The present disclosure relates generally to the field of electronics and, more particularly, to methods of forming integrated circuit devices. Background technique [0002] Hetero-integration of different semiconductor materials has been developed to improve the performance of integrated circuit devices. However, heterogeneous integration can lead to dislocation defects due to lattice mismatch-induced strain and may not improve performance. Contents of the invention [0003] A method of forming a semiconductor pattern may include: forming an oxide layer on a substrate; forming a recess in the oxide layer and the substrate; and forming an epitaxially grown semiconductor pattern in the recess, the semiconductor pattern contacting the substrate. The sidewalls at the interface between the oxide layer and the substrate, and may define the upper surface of the void within the recess in the substrate. [0004] According to various embodiments, forming an ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/02H01L21/20
Inventor W-E.王M.S.罗德R.C.伯温
Owner SAMSUNG ELECTRONICS CO LTD