Delay phase-locked loop circuit having start control function

Abstract

The invention discloses a delay phase-locked loop circuit having a start control function. The delay phase-locked loop circuit having the start control function comprises a phase detection sub-circuit, a voltage controlled delay chain, a first-order filter capacitor and a start control sub-circuit. The start control sub-circuit initializes control voltage and the control voltage is within the regulating range of delay control voltage of the voltage controlled delay chain. The phase detection sub-circuit regulates the value of the control voltage in accordance with the phase relationship between a reference clock and a feedback clock of the voltage controlled delay chain. The regulated control voltage serves as delay control voltage of the voltage controlled delay chain after filtered through the first-order filter capacitor for controlling the voltage controlled delay chain. According to the delay phase-locked loop circuit having the start control function, proper control voltage is set at the beginning of the working of the circuit, the delay of the voltage controlled delay chain on the reference clock is in half of the regulating range, the delay range provided by the voltage controlled delay chain is made full used, the locking speed of an entire system is accelerated, and meanwhile the chip area is not significantly increased.

Description

technical field [0001] The invention relates to the technical field of a delay phase-locked loop, and more specifically relates to a delay phase-locked loop circuit with a start-up control function. Background technique [0002] As the demand for chip performance continues to increase, on-chip clock distribution quality and clock delay become more and more important, and the requirements for suppressing clock skew and jitter are getting higher and higher. However, increases in clock frequency and circuit integration make it more difficult to reduce clock skew and jitter, whether the jitter is internal or from substrate or power supply noise. Traditional clock trees cannot maintain precise synchronization of on-chip high-speed clocks. In microprocessors, memory interfaces, and communication chips, a phase-locked loop (Phase Locked Loop, PLL) and a delay phase-locked loop (DLL) are generally used to implement clock synchronization. [0003] Among them, PLL is a high-level sy...

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Problems solved by technology

On the other hand, PLLs require complex second-order low-pass filters

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