A delay phase-locked loop circuit with start-up control function

Abstract

The invention discloses a delay phase-locked loop circuit with a start-up control function, comprising a phase detection sub-circuit, a voltage-controlled delay chain, a first-order filter capacitor and a start-up control sub-circuit; the start-up control sub-circuit initializes a control voltage, The control voltage falls within the adjustment range of the delay control voltage of the voltage-controlled delay chain; the phase detection sub-circuit unit adjusts the control voltage according to the phase relationship between the reference clock and the feedback clock of the voltage-controlled delay chain. The value of the voltage; the adjusted control voltage is filtered by the first-order filter capacitor and used as the delay control voltage of the voltage-controlled delay chain to control the voltage-controlled delay chain. The circuit of the present invention sets a suitable control voltage at the beginning of the circuit operation, so that the time delay of the voltage-controlled delay chain to the reference clock is half of its adjustment range, fully utilizes the delay range provided by the voltage-controlled delay chain, and speeds up The locking speed of the whole system is improved, and at the same time, the present invention does not significantly increase the chip area.

Description

technical field [0001] The invention relates to the technical field of a delay phase-locked loop, and more specifically relates to a delay phase-locked loop circuit with a start-up control function. Background technique [0002] As the demand for chip performance continues to increase, on-chip clock distribution quality and clock delay become more and more important, and the requirements for suppressing clock skew and jitter are getting higher and higher. However, increases in clock frequency and circuit integration make it more difficult to reduce clock skew and jitter, whether the jitter is internal or from substrate or power supply noise. Traditional clock trees cannot maintain precise synchronization of on-chip high-speed clocks. In microprocessors, memory interfaces, and communication chips, a phase-locked loop (Phase Locked Loop, PLL) and a delay phase-locked loop (DLL) are generally used to implement clock synchronization. [0003] Among them, PLL is a high-level sy...

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Problems solved by technology

On the other hand, PLLs require complex second-order low-pass filters

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