A Multiple Heuristic Instruction Selection Method for VLIW Architecture

Abstract

The invention discloses a multiple heuristic instruction selection method oriented to the VLIW architecture. The steps include: 1) Obtaining all transmittable instructions in the candidate instruction set of each functional unit, and the transmittable instructions are all instructions whose data-dependent instructions have been executed. ; 2) Separately calculate the multiple heuristics corresponding to each transmittable instruction in each functional unit, the heuristics include the dependency relationship between the instruction and the dependent instruction, the relationship between the instruction and the processing unit, and the relationship between the instruction and the functional unit. 3) Perform multiple sorting of the transmittable instructions in each functional unit, select a heuristic quantity as the sorting comparison quantity according to the priority order each time, and obtain the sorted transmittable command sequence as the instruction selection object . Aiming at the characteristics of the VLIW architecture, the invention fully considers the hardware characteristics between instructions and processing units and the correlation between data and functional units, and has the advantages of reasonable instruction selection and high parallelism.

Description

Technical field [0001] The invention relates to the technical field of compilation optimization of a VLIW (Very Long Instruction Word) architecture, in particular to a multiple heuristic instruction selection method oriented to the VLIW architecture. Background technique [0002] Basic block scheduling is one of the important processing processes to improve the instruction-level parallelism of the code. Under the premise of ensuring the same results, it can give full play to the performance of the hardware by rearranging the execution order of instructions, so it is a pipeline architecture or multi-function An important way to improve the efficiency of code execution in the unit’s super-long instruction word architecture. [0003] For the pipeline architecture, the basic block scheduling usually uses the table scheduling method. In the scheduling process using this method, two sequences need to be maintained: one is the scheduled (transmitted) node sequence Scheds; the other is eac...

AI Technical Summary

Problems solved by technology

[0017] To sum up, the above-mentioned instruction selection strategies for flow vector VLIW processors cannot well reflect the relationship between codes and functional units, nor can they reflect the execution characteristics of codes on the processor for a period of time, so they cannot fully Discover the parallelism of instructions in VLIW processors, while it is difficult to fully exploit the performance of the hardware

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