Multi-element heuristic instruction selecting method for VLIW system structure

Abstract

The invention discloses a multi-element heuristic instruction selecting method for a VLIW system structure. The method includes the steps of firstly, acquiring all transmittable instructions in the candidate instruction sets of functional units, wherein the transmittable instructions are instructions whose data dependence instructions are executed; secondly, calculating the multiple heuristic quantities corresponding to each transmittable instruction in each functional unit, and the heuristic quantities include the dependence relation quantity between each instruction and the corresponding dependence instruction, the relation quantity of between each instruction and a processing unit, and the relation quantity between each instruction and the corresponding functional unit; thirdly, sorting the transmittable instructions in each functional unit for multiple times, selecting one heuristic quantity as the sorting comparison quantity according to priority during each sorting, and using the transmittable instruction sequence after sorting as the instruction selecting object. The multi-element heuristic instruction selecting method has the advantages that the hardware feature between the instructions and the processing unit and the association between data and the functional units are fully considered aiming at the features of the VLIW system structure, and the method is reasonable in instruction selection and high in parallelism.

Description

technical field [0001] The invention relates to the technical field of compilation and optimization of a VLIW (Very Long Instruction Word, very long instruction word) architecture, in particular to a multiple heuristic instruction selection method oriented to the VLIW architecture. Background technique [0002] Basic block scheduling is one of the important processes to improve the instruction-level parallelism of the code. It can give full play to the performance of the hardware by rearranging the execution order of instructions under the premise of ensuring the same result. Therefore, it is a pipeline architecture or multi-function An important way to improve code execution efficiency in the VLW architecture of the unit. [0003] For the pipeline architecture, the basic block scheduling usually adopts the table scheduling method. In the scheduling process using this method, two sequences need to be maintained: one is the scheduled (transmitted) node sequence Scheds; the ot...

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Problems solved by technology

[0017] To sum up, the above-mentioned instruction selection strategies for flow vector VLIW processors cannot well reflect the relationship between codes and functional units, nor can they reflect the execution characteristics of codes on the processor for a period of time, so they cannot fully Discover the parallelism of instructions in VLIW processors, while it is difficult to fully exploit the performance of the hardware

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