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Voltage stabilizing circuit based on slew rate increasing

A voltage stabilizing circuit and slew rate enhancement technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve the problems of not responding immediately, not suitable for high power supply voltage linear regulators, etc., to simplify the circuit and optimize Output Transient Characteristics, Effect of High Supply Voltage Rejection Ratio

Active Publication Date: 2015-09-30
TECHTOTOP MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the slew rate enhancement circuit with the comparator as the core and the slew rate enhancement circuit with the differentiator as the core have different degrees of response delay, and cannot respond immediately after the LDO load jumps.
The existing zero-delay slew rate enhancement circuit can achieve zero-delay characteristics, but there are some defects and use limitations, such as: not suitable for high power supply voltage LDO circuits, additional linear regulators and additional feedback resistor networks are required.

Method used

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  • Voltage stabilizing circuit based on slew rate increasing
  • Voltage stabilizing circuit based on slew rate increasing
  • Voltage stabilizing circuit based on slew rate increasing

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Embodiment Construction

[0016] The solution of the present invention will be described in detail below in combination with the preferred embodiments thereof. The invention directly connects the output voltage VOUT to the grid stage of the M4 tube by using the capacitor device, so as to realize the zero-delay loop response. At the same time, M3, R1, and IB are used to provide static voltage bias for the gate of M4, and Native NMOS transistors M2 and C2 are used to provide static voltage bias for the source of M4 to ensure that the circuit achieves zero-delay loop response and has high performance. Power supply voltage rejection ratio, suitable for low input voltage application environment and other advantages. The output stage uses Native NMOS as the output power MOS tube, which has the advantage of obtaining a higher power supply voltage rejection ratio than the PMOS tube commonly used in existing solutions.

[0017] figure 2 A structural schematic diagram of a voltage regulator based on a slew ra...

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PUM

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Abstract

The invention discloses a voltage stabilizing circuit based on slew rate increasing. A capacitor device is utilized for directly connecting output voltage VOUT to an M4 transistor grid electrode, and zero-delay loop response is achieved. Quiescent voltage bias is provided for the M4 transistor grid electrode by means of M3, R1 and IB, quiescent voltage bias is provided with for an M4 transistor source electrode by means of a Native NMOS transistor, M2 and C2, it is ensured that the circuit achieves zero-delay loop response, and meanwhile the voltage stabilizing circuit has the advantages of being high in supply voltage rejection ratio, applicable to lower input voltage application environment and the like.

Description

technical field [0001] The invention relates to the field of hardware design, in particular to a voltage stabilizing circuit based on slew rate enhancement. Background technique [0002] In a low-power Capless Low Dropout Regulator (Capless LDO) system, there is generally a Slew Rate Enhancement Circuit (Slew Rate Enhancement Circuits, SRE) to enhance the LDO power when necessary. The charge and discharge current of the tube gate level, thereby improving the transient response characteristics of the LDO output voltage. [0003] figure 1 A general schema of the circuit block diagram of a Capless LDO is given. The main components of the circuit block diagram are: power MOS tube MPOW, feedback resistor network composed of RFB1 and RFB2, error amplifier, load impedance RL and CL, and slew rate enhancement circuit SRE. When the load current of the LDO changes suddenly or the output current of the power tube changes suddenly, the output voltage of the LDO fluctuates sharply, so...

Claims

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Application Information

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IPC IPC(8): G05F1/565
Inventor 朱吉涵
Owner TECHTOTOP MICROELECTRONICS
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