A Voltage Stabilizer Circuit Based on Slew Rate Enhancement

A voltage-stabilizing circuit and slew rate-enhancing technology, applied in the direction of regulating electrical variables, control/regulating systems, instruments, etc., can solve the problems of unsuitable linear voltage regulators with high power supply voltage and cannot respond immediately, and achieve optimal output transient Features, simplified circuit, area saving effect

CN104950976BActive Publication Date: 2017-05-17TECHTOTOP MICROELECTRONICS
6 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2017-05-17

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

The invention discloses a voltage stabilizing circuit based on slew rate increasing. A capacitor device is utilized for directly connecting output voltage VOUT to an M4 transistor grid electrode, and zero-delay loop response is achieved. Quiescent voltage bias is provided for the M4 transistor grid electrode by means of M3, R1 and IB, quiescent voltage bias is provided with for an M4 transistor source electrode by means of a Native NMOS transistor, M2 and C2, it is ensured that the circuit achieves zero-delay loop response, and meanwhile the voltage stabilizing circuit has the advantages of being high in supply voltage rejection ratio, applicable to lower input voltage application environment and the like.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the field of hardware design, in particular to a voltage stabilizing circuit based on slew rate enhancement. Background technique

[0002] In a low-power capless low dropout regulator (Capless Low Dropout Regulator, Capless LDO) system, there is generally a slew rate enhancement circuit (Slew Rate Enhancement Circuits, SRE), which is used to enhance the power of the LDO when necessary. The charge and discharge current of the tube gate level, thereby improving the transient response characteristics of the LDO output voltage.

[0003] figure 1 A general schema of the circuit block diagram of a Capless LDO is given. The main components of the circuit block diagram are: power MOS tube MPOW, feedback resistor network composed of RFB1 and RFB2, error amplifier, load impedance RL and CL, and slew rate enhancement circuit SRE. When the load current of the LDO changes suddenly or the output current of the power tube changes suddenly,...

Examples

Embodiment Construction

[0016] The solution of the present invention will be described in detail below in combination with the preferred embodiments thereof. The invention directly connects the output voltage VOUT to the grid stage of the M4 tube by using the capacitor device, so as to realize the zero-delay loop response. At the same time, M3, R1, and IB are used to provide static voltage bias for the gate of M4, and Native NMOS transistors M2 and C2 are used to provide static voltage bias for the source of M4 to ensure that the circuit achieves zero-delay loop response and has high performance. Power supply voltage rejection ratio, suitable for low input voltage application environment and other advantages. The output stage uses Native NMOS as the output power MOS tube, which has the advantage of obtaining a higher power supply voltage rejection ratio than the PMOS tube commonly used in existing solutions.

[0017] figure 2 A structural schematic diagram of a voltage regulator based on a slew ra...