Key node extraction method based on gate-level circuit simulation

A technology of gate-level circuits and key nodes, which is applied in the field of key node extraction of gate-level circuits, can solve problems such as high repetition rate, large search space, and high algorithm complexity, so as to speed up the recovery process, avoid repeated recovery, and improve search efficiency. efficiency effect
CN105956178BActive Publication Date: 2019-03-08XIDIAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
XIDIAN UNIV
Publication Date
2019-03-08

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Abstract

The present invention discloses a gate-level circuit simulation based key node extraction method. The method mainly solves the problems of low searching efficiency, inaccurate node state range restoration and an excessively high duplication rate in the prior art. The method comprises: acquiring a connection relationship of a gate-level circuit; by simulating the gate-level circuit, generating a state of a corresponding gate-level node, and calculating a ratio of states of key nodes 0 and 1; extracting a frequent subcircuit of the gate-level circuit; restoring, by D flip-flop DFF nodes extracted from the frequent subcircuit, a node of the gate-level circuit; in combination with the number of the node restored by the D flip-flop DFF nodes and the ratio of the states of 0 and 1, calculation weighted values, and extracting the D flip-flop DFF node with the greatest weighted value; and on the basis of the extracted D flip-flop DFF nodes, sequentially extracting subsequent key nodes. By use of the method disclosed by the present invention, the duplication rate of the the restored node is decreased, the searching efficiency is increased, the state range of the node stored by the key nodes is expanded, and the method can be used for error detection of the gate-level circuit, and tracking of internal signals is realized.
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Description

technical field

[0001] The invention belongs to the technical field of circuit processing, and in particular relates to a method for extracting key nodes of a gate-level circuit, which can be used to detect errors existing in the gate-level circuit and realize tracking of internal signals. Background technique

[0002] With the continuous improvement of chip scale and complexity, it takes too long to verify the correctness of the chip only by pre-silicon verification technologies such as simulation or formal verification, and it cannot fully guarantee the correctness of the first tape-out. In order to eliminate errors that cannot be found in the pre-silicon verification stage before the chip is released to the market, silicon debugging after the first tape-out is very necessary.

[0003] Silicon debugging technology is divided into two technologies based on the scan chain and based on the trace signal. The scan chain-based silicon debugging technology mainly captures the st...

Claims

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