Array substrate, liquid crystal display panel and method for manufacturing array substrate

Abstract

The invention provides an array substrate. The array substrate comprises a first metal layer formed on a substrate, an insulating layer, a TFT (thin film transistor) switch located on the insulating layer, a pixel electrode located on the insulating layer and connected with a drain electrode of the TFT switch, a first passivation layer covering the pixel electrode and a second metal layer located on the first passivation layer, wherein a via hole is formed in the first passivation layer, the second metal layer is connected with a source electrode of the TFT switch through the via hole, and the pixel electrode and the drain electrode and the source electrode of the TFT switch are formed on an ITO (indium tin oxide) material layer. A data line of the array substrate is formed on the pixel electrode, and then channel etching and manufacturing of the second metal layer are not in the same manufacture procedure in the manufacturing process, and furthermore in the process of manufacturing channels, electrostatic breakdown caused by hill bulges generated on the second metal layer is avoided. The invention further provides a liquid crystal display panel.

Description

technical field [0001] The invention relates to the technical field of display screens, in particular to an array substrate, a method for manufacturing the array substrate, and a liquid crystal display panel. Background technique [0002] Low temperature polysilicon (LTPS for short) thin film transistor liquid crystal displays are different from traditional amorphous silicon thin film transistor liquid crystal displays and are widely used. At present, in the manufacturing process of LTPS-TFT array substrate, because the design and process are carried out together, the current 5mask process sequence is to form M1 (first metal layer), G-SiNx (insulating layer) / a-Si (semiconductor layer) in sequence. / N, ohmic contact layer, M2 (second metal layer), PV passivation layer, ITO pixel electrode, the gate is made on the first metal layer, and the source and drain are made on the second metal layer. This design is in the channel During the etching process, because M2 is generally ma...

AI Technical Summary

Problems solved by technology

At present, in the manufacturing process of LTPS-TFT array substrate, because the design and process are carried out together, the current 5mask process sequence is to form M1 (first metal layer), G-SiNx (insulating layer) / a-Si (semiconductor layer) in sequence. / N, ohmic contact layer, M2 (second metal layer), PV passivation layer, ITO pixel electrode, the gate is made on the first metal layer, and the source and drain are made on the second metal layer. This design is in the channel During the etching process, because M2 is generally made of A1 material, A1 is prone to hillock protrusions, and M2 is prone to the risk of electrostatic discharge breakdown caused by tip power generation

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