A die seal interconnection substrate and a manufacturing method thereof
A technology for interconnecting substrates and molding, which is applied in the fields of printed circuit manufacturing, multilayer circuit manufacturing, semiconductor/solid-state device manufacturing, etc., and can solve problems such as drilling holes through the circuit layer and hole plating dissatisfaction
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no. 1 Embodiment
[0042] According to the first embodiment of the present invention, a molded interconnection substrate 100 is illustrated in figure 2 Schematic cross-sectional view and local enlarged view. A molded interconnection substrate 100 includes an embedded reconfiguration circuit layer 110, a plurality of first conductive pillars 120, a first chip 130, a first molded core layer 140 and a first embossed reconfiguration Line layer 150.
[0043] Such as figure 2 As shown, the embedded reconfiguration circuit layer 110 is formed on a molding plane 101, which can be provided by a temporary carrier 10 (such as Figure 3A As shown), the body of the temporary carrier 10 is glass or silicon, the shape can be a panel or a wafer, and a photosensitive adhesive layer can be formed on the surface of the body. The embedded reconfiguration circuit layer 110 includes a plurality of embedded circuits 111, a plurality of external pads 112 and a plurality of first internal pads 113, and the embedded...
no. 2 Embodiment
[0059] The molded interconnection substrate of the present invention can be not only a single-layer core structure, but also a multi-layer core structure. According to the second embodiment of the present invention, a molded interconnection substrate 200 is illustrated in Figure 4 A schematic cross-sectional view of the first specific embodiment, wherein the components corresponding to the same names and functions of the first specific embodiment are represented by the component figure numbers of the first specific embodiment, and the details of the same structure will not be repeated. A molded interconnection substrate 200 basically includes an embedded reconfiguration circuit layer 110, a plurality of first conductor pillars 120, a first chip 130, a first molded core layer 140 and a first embossed The line layer 150 is reconfigured.
[0060] Such as Figure 4 As shown, the embedded reconfiguration circuit layer 110 is formed on a molding plane 101, and the embedded reconf...
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