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Solid state disk hierarchical storage method and system

A hierarchical storage and solid-state hard disk technology, applied in the direction of input/output to record carrier, etc., can solve the problem of slow data reading and writing speed of TLC chip, achieve the effect of realizing flexibility and improving data reading speed

Inactive Publication Date: 2017-12-08
HUNAN GOKE MICROELECTRONICS
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  • Claims
  • Application Information

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Problems solved by technology

[0005] This application provides a method and system for hierarchical storage of solid-state hard disks to solve the problem of slow data read and write speed of TLC chips in the prior art

Method used

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  • Solid state disk hierarchical storage method and system
  • Solid state disk hierarchical storage method and system
  • Solid state disk hierarchical storage method and system

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Embodiment Construction

[0022] see figure 1 , is a flow chart of an embodiment of a solid state disk hierarchical storage method provided in this application. Such as figure 1 As shown, the method includes:

[0023] S101. Divide the TLC chip storage area into an SLC dynamic sub-storage area and a TLC dynamic sub-storage area.

[0024] Compared with SLC chips, TLC chips have a relatively larger storage capacity, but the data reading speed of TLC chips is slower and the number of erasures is less. Therefore, if the data in the TLC chip is erased many times, it will affect the service life of the TLC chip. . In the embodiment of the present application, the storage area of ​​the TLC chip is analogously divided into two independent dynamic areas: an SLC dynamic sub-storage area and a TLC dynamic sub-storage area. Among them, the SLC dynamic sub-storage area is used to store hot data during the data operation process of the solid-state disk, and the TLC dynamic sub-storage area is used to store cold d...

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Abstract

The embodiment of the invention discloses a solid state disk hierarchical storage method and system. The method includes the steps that a TLC chip storage region is divided into an SLC dynamic sub-storage region and a TLC dynamic sub-storage region; data block activeness in the SLC dynamic sub-storage region and the TLC dynamic sub-storage region is monitored according to preset data monitoring strength; the data activeness of data blocks in the SLC dynamic sub-storage region and the TLC dynamic sub-storage region is compared with a preset data activeness threshold value, and if the data migration condition is met, the data blocks in the SLC dynamic sub-storage region and the TLC dynamic sub-storage region are migrated. The TLC chip is dynamically divided, flexibility of TLC chip storage data is achieved, initial data is stored to the SLC dynamic sub-storage region, along with increase of read-in data, hot data and cold data are stored according to data activeness, data access is directly completed in the SLC dynamic sub-storage region, and therefore data read speed of the TLC chip is increased.

Description

technical field [0001] The present application relates to the technical field of solid-state hard disk storage, and in particular to a method and system for hierarchical storage of solid-state hard disks. Background technique [0002] A solid-state hard disk is a hard disk made of an array of solid-state electronic memory chips, consisting of a control unit and a storage unit (FLASH chip, DRAM chip). Among them, according to different FLASH chips, solid-state drives are divided into TLC (Triple-Level Cell, three-tier storage) solid-state drives and SLC (Single-Level Cell, single-tier storage) solid-state drives. Compared with SLC chips, TLC chips can achieve larger capacity and cheaper workmanship, so TLC chips are widely used in solid-state drives. [0003] However, SLC chips are much higher than TLC chips in terms of data read and write speed and service life, and not all data stored in solid-state drives have the same use value. As time goes by, some data is frequently u...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06
Inventor 陈友元姜黎彭鹏
Owner HUNAN GOKE MICROELECTRONICS
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