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Memorization body and operation method thereof

An operation method and memory technology, applied in the field of memory, can solve problems such as decreased reading efficiency and waste of system resources, and achieve the effect of reducing data gaps, avoiding waste, and improving data reading speed

Active Publication Date: 2008-10-01
NAN YA TECH
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, no matter whether the memory 110 reads data in the same memory bank 101-108 or different memory banks 101-108, there will be a data gap BUBBLE due to the column-to-column delay time tRRD being greater than tCCD, resulting in a read Fetching efficiency drops, wasting system resources

Method used

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  • Memorization body and operation method thereof
  • Memorization body and operation method thereof
  • Memorization body and operation method thereof

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Embodiment Construction

[0034] 3 is a memory architecture diagram according to an embodiment of the present invention. The memory 300 includes drive power 330, 340, and memory groups 310, 320, wherein the drive power 330 is coupled to the memory group 310, and the drive power 340 is coupled to the memory. Group 320. The memory group 310 includes memory banks A301-A304, and the memory group 320 includes memory banks B301-B304. In other words, the memory 300 divides the memory banks A 301 ˜ A 304 , B 301 ˜ 304 into two groups, and respectively configures different driving power sources 330 , 340 to provide the required operating voltage of the memory 300 in real time. The driving power sources 330 and 340 are independent voltage sources, but their power lines can be connected or independent. When the memory 300 needs to read the data in the memory storage banks A301-A304, the driving power supply 330 provides an operating voltage to the corresponding memory cells (memory cells) in the memory storage b...

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Abstract

The invention relates to a memory element and an operation method of the same. According to the invention, a plurality of memory storage libraries are divided into a plurality of memory groups, wherein, each memory group is equipped with an independent driving power supply for providing an operation voltage to the corresponding memory storage library. Two kinds of row-to-row relay time are set as an external interval and an internal interval respectively. A minimal interval of one row to another row in a same memory group is selected as the internal interval, a minimal interval between rows of different memory groups is selected as the external interval, wherein the external interval is less than or equal to the internal interval. The memory element of the invention is capable of improving data reading speed of the memory element, reducing generation of data slots, and avoiding waste of system data.

Description

technical field [0001] The present invention relates to a memory, and in particular to a dynamic random access memory (DRAM) with different row-to-row delay (tRRD time for short) and its operation method. Background technique [0002] Conventional semiconductor memory devices generally include a plurality of memory banks, wherein each memory bank has the same capacity (that is, the same number of memory cells) and the same storage capacity. In particular, the current standard memory architecture commonly used for dynamic random access memory (DRAM) generally includes a plurality of memory banks of equal capacity. Such as figure 1 as shown, figure 1 It is a DRAM architecture diagram according to the prior art. The memory 100 includes a memory unit 110 and a drive power supply 120, wherein the memory unit 110 includes memory storage banks 101-108. When the system selects a row (Row) in the memory 100, the drive power supply 120 provides voltage to drive the corresponding c...

Claims

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Application Information

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IPC IPC(8): G11C11/406G11C11/4063
Inventor 张全仁刘维理
Owner NAN YA TECH
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