A method for controlling power on and off, main controller and system

Abstract

The invention discloses a method for controlling power on and off, a main controller and a system. The method includes: the main controller sends the power on and off control information for controlling the slave controller to the second serial port of the integrated south bridge PCH, and the main controller The complex programmable logic device CPLD on the controller reads the power-on and power-off control information through the low pin count LPC interface, and sends the power-on and power-off control information to the CPLD on the slave controller; the first of the PCH The serial port corresponds to print log information; so that the CPLD of the slave controller controls the power-on or power-off of each DC-DC converter DC-DC converter on the slave controller according to the power-on and power-off control information. The method can control the power-on or power-off of each DC-DC converter DC-DC converter on the slave controller in real time according to the power-on and power-off control information of the master controller.

Description

technical field [0001] The invention relates to the technical field of chip power supply control, in particular to a method for controlling power on and off, a main controller and a system. Background technique [0002] At present, the architecture of dual-terminal controllers is often used in storage systems to provide controller redundancy and ensure data security, so information exchange and synchronization between dual-terminal controllers is very important. Double-ended controllers generally include a master controller and a slave controller. The information channel between the master controller and the slave controller is more common PCIe (Peripheral Component Interconnect Express, high-speed external device interconnection) NTB (Non-transparent bridging, non-transparent bridging). [0003] see figure 1 , which is a common frame diagram of a master controller and a slave controller in the prior art. [0004] Wherein, the first CPU 101 is connected to the non-transpa...

AI Technical Summary

Problems solved by technology

It should be noted that the data transmitted using PCIe is actually transmitted between the first CPU 101 and the second CPU 102, which belongs to the interaction of upper-level information, and in order to realize the lower-level requirements such as power on and off of a single controller, it is necessary to Carrying out high-investment and high-time-consuming software development work is often not worth the candle

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