Acceleration card based on CPLD, data acquisition method and device

Abstract

The invention discloses an acceleration card based on CPLD, comprising: a CPLD chip arranged on the acceleration card; One end of the CPLD chip is connected with the BMC chip of the host terminal, andthe other end is connected with each data acquisition device on the acceleration card, which is used for sending the data of each data acquisition device to the BMC chip. Therefore, in this scheme, through the CPLD chip set in the accelerator card to collect the data of each data acquisition equipment, on the basis of the data collection, the acceleration function of the accelerator card is not affected, upgrading and maintenance are facilitated; Moreover, if the CPLD chip is set on the acceleration card, the size of the card, the difficulty of development and the power consumption do not have a great impact on the acceleration card. The invention also discloses an acceleration card data acquisition method and a device, which can also realize the technical effect.

Description

technical field [0001] The invention relates to the technical field of accelerator card information collection, and more specifically, to a CPLD-based accelerator card, a method and a device for collecting accelerator card data. Background technique [0002] With the rapid development of artificial intelligence technology and high-performance computing and the explosive growth of big data, traditional processor chips have encountered great challenges in improving the performance-to-power ratio. In order to achieve faster computing speed and lower power consumption, accelerator cards based on FPGA (Field Programmable Gate Array, Field Programmable Gate Array) emerged as the times require. FPGA is characterized by its high performance, high density, low latency and hardware programmable And other characteristics, gradually occupy the accelerator card market. The accelerator card is usually connected to the server through the PCIe interface. As a subsystem of the server, it is...

AI Technical Summary

Problems solved by technology

However, this solution using FPGA will undoubtedly increase the workload of the FPGA. For the FPGA chip used to increase the calculation speed, its main function is to process data interaction with the CPU and complete the calculation of the algorithm, thereby increasing the calculation speed of the CPU.

If the sensor data acquisition and transmission functions that are not related to the acceleration function are added, the precious resources of the FPGA will be wasted, the convergence of the FPGA timing will be affected, and it is not conducive to upgrades and maintenance

For the method of using other processors, developers need to apply another chip or another language technology, and developers need to be added

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