Sequencing statistical decoding method assisted by partial cyclic redundancy check

A technology of cyclic redundancy check and check code, which is applied in the application of error detection coding of multiple parity bits, error correction/detection, and coding using block codes, and can solve the problem of small performance gain and damage to LDPC codes. High-speed decoding characteristics and other issues to achieve the effect of improving performance

Active Publication Date: 2019-07-05
SOUTHEAST UNIV
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Problems solved by technology

Since the complexity of the OSD decoding method is proportional to N 2 , OSD decoding is performed on the output soft information of each iteration, which will add a lot of delay to each iteration and destroy the high-speed decoding characterist

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  • Sequencing statistical decoding method assisted by partial cyclic redundancy check
  • Sequencing statistical decoding method assisted by partial cyclic redundancy check
  • Sequencing statistical decoding method assisted by partial cyclic redundancy check

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Embodiment Construction

[0127] Below in conjunction with accompanying drawing, the present invention is further described:

[0128] The object of the present invention is to provide a sorting statistical decoding method assisted by a partial cyclic redundancy check. The verified generator polynomial forms the system generator matrix, and divides the matrix into two parts, one part is used to detect the decoding result, and the other part is used for auxiliary decoding; The joint generator matrix is ​​obtained by multiplying the generator matrices; in the iterative decoding process, the reliability of the node is defined according to the magnitude of the cumulative value of the likelihood ratio output by all variable nodes in previous iterations, and the nodes and the columns of the above joint generator matrix are calculated according to the degree of reliability. Perform descending sorting, and perform Gaussian elimination on the column-sorted matrix; combine the joint system generated matrix obtain...

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Abstract

The invention discloses a sequencing statistical decoding method assisted by partial cyclic redundancy check (CRC). The method is suitable for soft decision decoding of low-density parity check (LDPC)codes with information bits meeting CRC. Before decoding, a system generation matrix is formed according to a generation polynomial of cyclic redundancy check, the matrix is divided into two parts, one part is used for detecting a decoding result, and the other part is used for assisting decoding. A part of the CRC generation matrix of auxiliary decoding is multiplied by the generation matrix ofthe low-density parity-check code to obtain a joint generation matrix. In the decoding process, an iterative sorting statistical decoding (BP-OSD) method is mainly adopted, and a matrix is generated jointly to serve as a coding matrix in an OSD algorithm. After decoding is completed, CRC check is conducted on the information bits of the code words, and if the CRC check is met, the code serves as decoding output; otherwise the code is decided as decoding failure. According to the method, the error correction performance of the LDPC code is greatly enhanced while the CRC error detection functionis reserved.

Description

technical field [0001] The invention belongs to the technical field of decoding of channel error correction coding, in particular to the technical field of decoding of channel error correction coding. Background technique [0002] 1. Cyclic redundancy check code [0003] A cyclic redundancy check code (Cyclic Redundancy Check, CRC) is a very important error detection code, which is not only simple in encoding, but also has a low probability of misjudgment. CRC is essentially to generate a check code (CRC code) of length L according to certain rules from an input sequence of length K, and add it to the back of the original sequence to form a new sequence of length K+L and send it out. . The receiving end checks the received sequence according to the same rules to find out whether there is an error in data transmission. This rule is called "generator polynomial" in error control theory. The main function of CRC is to detect whether there is a bit error in the transmission ...

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Application Information

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IPC IPC(8): H03M13/11H03M13/00
CPCH03M13/1125H03M13/6502H03M13/1148
Inventor 姜明李政熠赵春明
Owner SOUTHEAST UNIV
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