Fast universal acquisition device and method for drone image transmission and remote control signal

Abstract

The invention discloses a fast universal acquisition device and method for drone image transmission and a remote control signal. The device comprises an FPGA board, an AD9361 daughter board connectedto the FPGA board through an FMC connection mode, and a Gigabit Ethernet port expansion board connected to the FPGA board through an IO two-way connection mode, wherein the FPGA board is externally connected with a PC end through the serial port. The method comprises the following steps of 1) initialization of AD9361 through the control of FPGA; 2) dual-channel fixed-frequency and wideband sweep acquisition of AD9361; 3) data acquisition for multiple-channel distribution; 4) FFT processing of the acquired data; 5) 8-channel data asynchronous storage and transmission; 6) temperature control protection processing of the FPGA board; and 7) Gigabit network transmission of the acquired data. The device is low in cost, easy to implement, good in real-time, versatile, and simple to operate. The method can perform fixed-frequency acquisition of 70MHZ to 6GHZ wireless signals, perform fast frequency sweep acquisition on frequency bands of common image transmission and remote control signals ofthe drone, and perform storage as well as 8-channel asynchronous simultaneous reading and writing on the acquired large-scale real-time data.

Description

technical field [0001] The invention relates to the field of radio technology, in particular to a fast and general acquisition device and acquisition method for UAV image transmission and remote control signals. Background technique [0002] At present, the main device used for the acquisition of UAV image transmission and remote control signals is the Zedboard development board of Xilinx Company and the AD9361 daughter board of ADI Company. The Zedboard development board is mainly composed of ZYNQ series FPGA chips, Gigabit Port chip, DDR memory stick, serial port chip and so on. The development steps are mainly that the PC side sends the registers of the AD9361 chip to the PS side of ZYNQ through the serial port, and then the PS side transmits the data to the PL side through the AXI timing sequence, and the PL side uses the FMC interface to configure the registers to the AD9361 chip through the SPI timing sequence to realize After data acquisition, the collected data is t...

AI Technical Summary

Problems solved by technology

[0003] For the above method, from the perspective of system transplantation, this method is limited to ZYNQ models and other integrated ARM series chips, and cannot be transplanted to pure logic conventional FPGAs; from the perspective of logic resources and labor costs, the internal logic resources of ZYNQ and PL terminal IO It is not too sufficient, and developers have high requirements. They must be familiar with ARM operations and FPGA operations, and the cost is relatively high; from the perspective of the overall system operating speed, this method stores PL terminal data into the PS terminal through the PS terminal. DDR, which is read out by the PS side, requires the cooperative processing of FPGA and ARM. Compared with the pure logic FPGA, which uses a fully parallel method to collect, store, and transmit data, the development speed of ZYNQ is relatively slow; for the frequency sweep method, The commonly used PS terminal controls the PL terminal, and then the PL terminal controls the AD9361 frequency sweep method, which is not too fast; for the storage method, the single-channel storage and read-write method does not require simultaneous storage and readout of multiple channel data. It is easy to meet, and the real-time performance is relatively low, so a new collection, storage, and transmission method is needed to solve the shortcomings of this method

Images