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FPGA-based financial data flow control device and flow control method

A data flow and financial technology, applied in the direction of electronic digital data processing, instruments, etc., can solve the problems of lowering the upper limit of server pressure, increasing CPU processing burden, and inappropriate delay sensitive occasions, so as to avoid data loss, strong dynamic adjustment, Effect of unloading server load

Active Publication Date: 2019-10-01
上海仪电(集团)有限公司中央研究院 +1
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

However, the cost of local caching is to prepare and consume a large amount of local storage space, and additionally increase the burden of CPU processing, reducing the upper limit of pressure on the server; distributed caching will introduce huge network delays, which is not suitable for some delay-sensitive occasions

Method used

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  • FPGA-based financial data flow control device and flow control method
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  • FPGA-based financial data flow control device and flow control method

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Embodiment Construction

[0040] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is carried out on the premise of the technical solution of the present invention, and detailed implementation and specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.

[0041] In order to reduce the additional delay and unload the server load, the present invention provides an FPGA-based financial data flow control device, which uses FPGA to replace some functions of the software processing solution, analyzes network packet data at the physical layer, and stores specific data packets in DDR RAM , and read from DDR RAM at an appropriate release speed and send it to the server via PCIe.

[0042] Such as figure 1 As shown, the flow control device includes an FPGA acceleration board, and the FPGA acceleration board includes a physical layer interface mo...

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Abstract

The invention relates to an FPGA-based financial data flow control device and a flow control method, the flow control device comprises an FPGA acceleration board card, and the FPGA acceleration boardcard comprises a physical layer interface module which is used for obtaining network packet data and analyzing the network packet data on a physical layer; a data packet identification module which isused for identifying a data packet type according to an analysis result; a path judgment module which is used for selecting a transmission path according to the type of the data packet, wherein the transmission path comprises a cache path and an uploading path; a caching module which is used for caching the data packets belonging to the caching path; and a DMA module which is used for uploading the data packet belonging to the uploading path to the server. Compared with the prior art, additional network delay is greatly reduced while the CPU load of the server is unloaded, and the method hasthe advantages of being flexible, wide in application range and the like.

Description

technical field [0001] The invention relates to the technical field of financial data flow control, in particular to an FPGA-based financial data flow control device and flow control method. Background technique [0002] With the rapid development of network technology, more and more network-based applications are becoming more and more complex. The development of network technology has not only improved productivity and brought about a rise in the stock market, but also established a complete IT system for the financial industry. The continuous innovation of financial tools and the successive emergence of financial derivatives such as futures and options have brought about the emergence of profit opportunities such as arbitrage and trend manipulation in the market. Faced with a large amount of complex financial information, quantitative investment and programmatic transaction data, the next generation computer must have PB / s (PetaByte) level data processing capabilities to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/12G06F13/42
CPCG06F13/122G06F13/4282Y02D10/00
Inventor 左佳应根军方逸洲胡放明
Owner 上海仪电(集团)有限公司中央研究院
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