3D NoC test scheduling method based on Petri network and IFA

Abstract

The invention discloses a 3D NoC test scheduling method based on a Petri network and an IFA. On one hand, according to the characteristics that IP core test processes are similar, TAM selection is random, and the routing process is tedious in the test scheduling process; a Petri net model is divided into an upper layer and a lower layer, the modeling process is simplified, model elements are reduced through the coloring thought, the net scale is compressed, and the characteristics such as the test scheduling process, the resource constraint and the priority of an IP core in 3D NoC are accurately described; on the other hand, route calculation change in the model is improved, so that dual optimization of the system test time in the aspects of scheduling combination and routing process is realized; besides, IFA is embedded into the model, powerful algorithm support is provided for model solving, the optimal test scheduling scheme can be efficiently obtained accordingly, the test time isshortened by about 8.94% compared with other methods, and the test efficiency is effectively improved.

Description

technical field [0001] The invention relates to the technical field of three-dimensional network-on-chip (3D NoC), in particular to a 3D NoC test scheduling method based on Petri net and IFA. Background technique [0002] 3D NoC (Three-Dimensional Network on Chip), as a highly integrated, multi-processor system based on network architecture, combines the advantages of planar NoC (Network on Chip) and three-dimensional stacking technology, and gradually becomes the main development trend of integrated circuits in the future. At the same time, users continue to put forward more requirements for chip system functions, so the number of IP cores (Intellectual Property Cores) integrated in 3D NoC has doubled, and the interconnection structure between IP cores has also become more complex, resulting in the use of guarantees. Chip testing for product yield is facing more challenges. Exploring efficient test scheduling optimization methods is of great significance for reducing chip ...

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