3D NoC test scheduling method based on petri net and ifa

A test scheduling, 3dnoc technology, applied in instruments, artificial life, computing, etc., can solve problems such as low IP core test efficiency, and achieve the effect of enhancing model description ability, high scheduling efficiency, and short test time

Active Publication Date: 2022-02-18
GUILIN UNIV OF ELECTRONIC TECH
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AI Technical Summary

Problems solved by technology

[0004] What the present invention is to solve is the problem that the IP core test efficiency in 3D NoC exists in the existing 3D NoC test scheduling method, and a 3D NoC test scheduling method based on Petri net and IFA is provided

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  • 3D NoC test scheduling method based on petri net and ifa
  • 3D NoC test scheduling method based on petri net and ifa
  • 3D NoC test scheduling method based on petri net and ifa

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Embodiment Construction

[0047]In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific examples.

[0048] The present invention mainly conducts research from the following three aspects: the establishment of a visual model of test scheduling, the optimization of the routing process combined with the characteristics of the 3D Torus topology, and the improvement of the model solving algorithm. The technical problem of low efficiency of IP core testing.

[0049] Since there are interconnection lines between any two end nodes in the NoC of the 3D Torus topology, the resources available for testing are more abundant than those of the 3D Mesh topology, which can reduce network congestion. Therefore, the 3D NoC of the Torus structure is selected for research. 3D NoC with Torus structure of 3*3*3 such as figure 1 As shown, the figure shows the composition and interconnection o...

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Abstract

The invention discloses a 3D NoC test scheduling method based on Petri net and IFA. On the one hand, the Petri net model is divided into upper and lower two according to the similar characteristics of each IP core test process in the test scheduling process, random TAM selection, and cumbersome routing process. layer, which simplifies the modeling process, and reduces the model elements through the coloring idea, compressing the network scale, so that the test scheduling process, resource constraints, priority and other characteristics of the IP core in the 3D NoC can be accurately described; on the other hand, the model In order to improve the routing calculation transition in the system, the dual optimization of the system test time in terms of scheduling combination and routing process is realized; in addition, IFA is embedded in the model, which provides powerful algorithm support for the model solution, so that the optimal solution can be efficiently obtained. The test scheduling scheme, and the test time is shortened by about 8.94% compared with other methods, which effectively improves the test efficiency.

Description

technical field [0001] The invention relates to the technical field of three-dimensional network-on-chip (3D NoC), in particular to a 3D NoC test scheduling method based on Petri net and IFA. Background technique [0002] 3D NoC (Three-Dimensional Network on Chip), as a highly integrated, multi-processor system based on network architecture, combines the advantages of planar NoC (Network on Chip) and three-dimensional stacking technology, and gradually becomes the main development trend of integrated circuits in the future. At the same time, users continue to put forward more requirements for chip system functions, so the number of IP cores (Intellectual Property Cores) integrated in 3D NoC has doubled, and the interconnection structure between IP cores has also become more complex, resulting in the use of guarantees. Chip testing for product yield is facing more challenges. Exploring efficient test scheduling optimization methods is of great significance for reducing chip ...

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H04L41/14H04L43/08H04L45/02H04L45/121G06N3/00
CPCH04L41/145H04L41/0823H04L43/08H04L45/02H04L45/121G06N3/006
Inventor胡聪郑岚周甜朱爱军许川佩陈涛万春霆张本鑫
OwnerGUILIN UNIV OF ELECTRONIC TECH