Multiplying device, data processing method, chip and electronic equipment

A multiplier and data technology, applied in the computer field, can solve the problem of high complexity of multiplication operations, and achieve the effect of reducing complexity and number

Pending Publication Date: 2019-11-29
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the traditional technology, the number of non-zero bit values ​​in the code is large, and the number of correspondi

Method used

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  • Multiplying device, data processing method, chip and electronic equipment
  • Multiplying device, data processing method, chip and electronic equipment
  • Multiplying device, data processing method, chip and electronic equipment

Examples

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Embodiment Construction

[0056] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0057] The multiplier provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing. The specific structural diagram is as follows figure 1 and 2 shown.

[0058] figure 1 A specific structural schematic diagram of a multiplier provided for an embodiment, such as figure 1 As shown, the multiplier includes: a regular signed number encoding circuit 11, a modified partial product acquisition circuit 12, a Wallace tree circuit 13 and an a...

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Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: a regular sign number coding circuit, a corrected partial product acquisitioncircuit, a correcting Wallace tree group circuit and an accumulation circuit; the output end of the regular signed number encoding circuit is connected with the input end of the correction partial product acquisition circuit; the output end of the correction partial product acquisition circuit is connected with the input end of the correction Wallace tree group circuit; according to the multiplier, regular signed number encoding can be carried out on received data through the regular signed number encoding circuit, the number of obtained effective partial products is small, and therefore the complexity of multiplication operation of the multiplier is lowered.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm. [0003] At present, the multiplier uses every three-digit value in the multiplier as a code, and obtains partial products according to the multiplicand, and uses Wallace tree to compress all partial products to obtain the result of multiplication. However, in the conventional technology, the number of non-zero bit values ​​in the code is large, and the number of corres...

Claims

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Application Information

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IPC IPC(8): G06F7/53G06F7/533G06F7/48G06N3/063
CPCG06F7/5318G06F7/5332G06F7/4824G06N3/063
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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