Multiplying device, data processing method, chip and electronic equipment

Abstract

The invention provides a multiplier, a data processing method, a chip and electronic equipment. The multiplier comprises: a regular sign number coding circuit, a corrected partial product acquisitioncircuit, a correcting Wallace tree group circuit and an accumulation circuit; the output end of the regular signed number encoding circuit is connected with the input end of the correction partial product acquisition circuit; the output end of the correction partial product acquisition circuit is connected with the input end of the correction Wallace tree group circuit; according to the multiplier, regular signed number encoding can be carried out on received data through the regular signed number encoding circuit, the number of obtained effective partial products is small, and therefore the complexity of multiplication operation of the multiplier is lowered.

Description

technical field

[0001] The present application relates to the field of computer technology, in particular to a multiplier, a data processing method, a chip and electronic equipment. Background technique

[0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance digital multipliers. The neural network algorithm is one of the algorithms widely used in smart chips, and the multiplication operation through the multiplier is a common operation in the neural network algorithm.

[0003] At present, the multiplier uses every three-digit value in the multiplier as a code, and obtains partial products according to the multiplicand, and uses Wallace tree to compress all partial products to obtain the result of multiplication. However, in the conventional technology, the number of non-zero bit values ​​in the code is large, and the number of corres...

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