Digital control wide-range clock duty ratio adjusting system

Abstract

The invention provides a digital control wide-range clock duty ratio adjusting system. The system comprises differential clock input signals clkinp and clkinn which are transmitted in a full-swing digital signal form, a forward path which is composed of a digital logic unit CMOS inverter and a duty ratio adjusting circuit, and a feedback loop which is connected with output clock signals clkoutp and clkoutn and the duty ratio adjusting circuit. According to the invention, the whole loop is digitally controlled; the power consumption of the system is greatly reduced, and the numerical control duty ratio adjusting circuit can achieve a wider adjusting range; an error elimination circuit adopted in the loop not only can eliminate offset voltage brought by a chip process; and a fully differential structure is adopted, so that the adjustment precision of the system is further improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a digitally controlled wide-range clock duty ratio adjustment system. Background technique [0002] With the continuous development of communication technology and integrated circuit technology, the requirements for the amount of information transmission are also increasing. Parallel transmission seriously affects the transmission speed. Serial communication technology has become the mainstream technology of high-speed circuit interface, and serial communication technology requires high-speed Clock data, so the working speed of the chip continues to increase. On the one hand, the higher rate requires the system to meet more stringent timing, and the performance of the clock becomes the bottleneck of the system performance; on the other hand, the higher the rate, the more difficult the design. In order to avoid the above-mentioned problems, the half-rate st...

AI Technical Summary

Problems solved by technology

Although this reduces the clock rate, it also introduces new problems: the duty cycle of the clock becomes a more important performance index, and the duty cycle jitter of the high-speed clock will seriously affect the system performance and make the system unstable.

The duty ratio adjustment loop proposed in this patent also uses an analog feedback loop to adjust the duty ratio. The adjustme

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