Craft imbalance non-sensitive cyclic analog-digital converter and conversion method

Abstract

The invention relates to the field of integrated circuit design of microelectronics. The craft imbalance non-sensitive circulating type analog-digital converter and a conversion method aim to reduce sensitiveness of cyclic analog-digital converter (Cyclic ADC) to craft imbalance and improve the linearity of the Cyclic ADC. The technical scheme includes that a multiplication digital-analog converter conducts operation of analog-digital conversion and circulation and timing 2 circularly, according to the craft imbalance non-sensitive circulating type analog-digital converter, the craft imbalance non-sensitive circulating type analog-digital converter further comprises a digital correcting circuit and a register, the multiplication digital-analog converter comprises a 1.5-bit secondary ADC, a digital to analog converter (DAC), linked switches (S1-S3), linked switches (Sw1-Sw2), and capacitors (C1P, C1N, C2P, C2N, C3P, C3N). The craft imbalance non-sensitive circulating type analog-digital converter and the conversion method are mainly applied to the integrated circuit design.

Description

technical field [0001] The invention relates to the field of integrated circuit design of microelectronics, in particular to a non-sensitive circulation analog-to-digital converter and a conversion method of process imbalance. Background technique [0002] Cyclic ADC (Cyclic Analog-to-Digital Converter, Cyclic Analog-to-Digital Converter) has the advantages of simple structure, high speed, low power consumption and small area, and it is widely used in various sensor readout circuits, such as CMOS image sensor. The equivalent circuit structure of a Cyclic ADC that outputs 1.5 bits per cycle is as follows figure 1 As shown, the analog input signal is converted by MDAC (Multiplying Digital-to-analog, multiplication digital-to-analog converter) for analog-to-digital conversion and cycle multiplication by 2, and all the digital signals output by cycle are processed by RSD (Redundant Signed Digit) digital correction circuit It is restored to the final converted digital signal, a...

AI Technical Summary

Problems solved by technology

The multiplication by 2 circuit is generally implemented by a switched capacitor circuit, where the mismatch of the capacitance will affect the accuracy of the multiplication by 2

With the reduction of the feature size of the integrated circuit process, the power consumption of the integrated circuit is also gradually reduced, but the mismatch of the device becomes more serious, which further deteriorates the gain accuracy of the multiply-by-two circuit in the Cyclic ADC, thereby reducing the Linearity of Cyclic ADC

In the prior art, digital calibration can be used to solve the problem of device mismatch, but this will inevitably increase the scale and complexity of the digital circuit

The Cyclic ADC offset elimination method provided by the prior art is to store the negative offset voltage in the cross-connection of the feedback capacitor, and then superimpose and eliminate it with the positive offset of each cycle. This method can change the equivalent input offset voltage of the Cyclic ADC to is approximately 0, but there are positive and negative feedback loops in the system in the imbalance storage stage, and the negative feedback must be stronger than the positive feedback system to be stable, so there are unstable factors in the system, which reduces the stability of the system

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