Unlock instant, AI-driven research and patent intelligence for your innovation.

Circuit gate size optimization method based on network topology sequence

A network topology and size optimization technology, applied in the direction of constraint-based CAD, electrical digital data processing, special data processing applications, etc., can solve problems such as rounding of solution results, time-consuming increase, and deterioration of solution results, so as to ensure optimal results , the effect of improving the solution speed

Active Publication Date: 2021-11-19
南京集成电路设计服务产业创新中心有限公司
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The method based on the assumption of continuous door size has an elegant expression in mathematics, but the solution results face the problem of rounding
The strict rounding algorithm will significantly increase the time consumption, and the simple rounding method often leads to the deterioration of the solution results

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Circuit gate size optimization method based on network topology sequence
  • Circuit gate size optimization method based on network topology sequence
  • Circuit gate size optimization method based on network topology sequence

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] figure 1 For the flow chart of the method for optimizing the size of circuit gates based on network topology order according to the present invention, reference will be made below figure 1, to describe in detail the gate size optimization method based on the network topology order of the present invention.

[0041] First, in step 101, at the beginning of the process, the entire circuit design is input, and the overall circuit is divided into multiple parts according to the connection relationship of the circuit.

[0042] Preferably, starting from the input signal end of the path, the output end connected to it and the network where the output end is located are included in the same group until the end of the path.

[0043] In this embodiment, with figure 2 Take the circuit shown in (a) as an example, A and B terminals are the signal input directions. Start from the starting end A of one of the paths, go through the signal line W21 to the CK terminal of the register ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A circuit gate size optimization method based on a network topology sequence comprises the following steps: grouping overall circuits according to a connection relation of the circuits; after grouping is completed, optimizing the circuit of each group; and combining the optimization processing results of the respective grouped circuits, and applying a replacement circuit unit to the whole circuit to complete the gate size optimization of the whole circuit. According to the circuit gate size optimization method based on the network topology sequence, the optimization precision is ensured, the problem that the result needs to be rounded by a traditional optimization algorithm based on a mathematical form is avoided, and meanwhile the solving speed of the gate size optimization problem is increased.

Description

technical field [0001] The present invention relates to the technical field of electronic design automation (Electronic Design Automation, EDA), in particular to a discrete gate size (Gate Sizing) optimization algorithm based on network topology order. Background technique [0002] EDA (Electronic Design Automation) uses a series of software tools to complete the automated design of electronic systems such as integrated circuits with the help of electronic computers. Its main goal is to convert a high-level hardware description language into an achievable circuit design that satisfies a series of constraints such as timing, power consumption, and area under the premise of correct function. EDA tools have greatly improved the efficiency of circuit design, shortened the design cycle, and saved design costs. As the scale of integrated circuits continues to grow, how to quickly and reliably convert high-level descriptions into circuits has become a major challenge in the EDA fi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F30/392G06F30/398G06F111/04
CPCG06F30/392G06F30/398G06F2111/04
Inventor 叶旻渊陈刚
Owner 南京集成电路设计服务产业创新中心有限公司