Processor unit for multiplication and accumulation operations

A technology of processor unit and accumulator, applied in electrical digital data processing, instruments, memory systems, etc., can solve problems such as resource-intensive, and achieve the effect of less wiring, small footprint, and reduced energy consumption

Pending Publication Date: 2022-07-12
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, conventional electronic systems for computing MAC operations can be resource intensive

Method used

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  • Processor unit for multiplication and accumulation operations
  • Processor unit for multiplication and accumulation operations
  • Processor unit for multiplication and accumulation operations

Examples

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Embodiment Construction

[0034] The descriptions of various embodiments of the present invention are presented for purposes of illustration, and are not intended to be exhaustive or limited to the disclosed embodiments. Numerous modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand.

[0035]According to one embodiment, each of the MAC units is associated with an index, wherein the MAC unit is configured to perform a MAC operation by executing a processor instruction referencing the index. This enables the identification of a specific MAC unit to best handle the instruction by reading the instruction's index. This may be optimal since such reads are perform...

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Abstract

There is provided a processor unit for multiply and accumulate ("MAC") operations, the processor unit comprising: a plurality of MAC units for performing a set of MAC operations, where each MAC unit of the plurality of MAC units comprises an execution unit and a write-once-read ("1W/1R") register file, where the 1W/1R register file has at least one accumulator; the execution unit of each MAC unit is configured to execute the set of MAC operations by calculating a product of a set of values received from the other register file and adding the calculated product to the content of at least one accumulator, wherein each MAC unit is configured to perform the respective subset of MAC operations in a single clock cycle.

Description

technical field [0001] The present invention relates to the field of digital computer systems, and more particularly to a processor unit for performing a set of one or more multiply and accumulate ("MAC") operations. Background technique [0002] The computation of MAC operations is commonly used in many algorithms, such as the training of deep neural networks, image processing, and other machine learning techniques. For example, in the case of deep neural networks, MAC operations can involve activations and gradients. However, conventional electronic systems for computing MAC operations can be resource intensive. In particular, there is a need for an energy efficient and resource saving architecture for performing such operations. SUMMARY OF THE INVENTION [0003] Different embodiments provide a processor unit, method, computer program product and MAC unit for performing a set of one or more MAC operations as described by the subject matter of the independent claims. A...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/302
CPCG06F9/3001G06F9/3851G06F9/30036G06F9/3889G06F9/3893G06F9/30101G06F9/3887
Inventor J·莱恩斯塔拉A·瓦格纳J·莫雷拉B·汤普托
Owner IBM CORP
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