Method for making mask read-only memory

Abstract

A method of fabricating a mask ROM comprising: preparing a substrate defined by a memory cell array region and a peripheral region; forming a device isolation film between the memory cell array region and the peripheral region; forming a gate-forming material layer; covering the memory cell array region and selectively etching the gate-forming material layer in the peripheral region to form a first gate; forming an insulation spacer in a lateral portion of the gate; injecting ion to the substrate in the peripheral region to form a source / drain region; forming salicide on the gate-forming material layer of the memory cell array region and the gate and in the source / drain region; covering the peripheral region and selectively etching the gate-forming material layer in the memory cell array region to form a second gate; and forming a protective film on the resultant substrate.

Description

technical field [0001] The present invention relates to the manufacturing method of mask read-only memory, relate to more specifically the dual gate (dual gate) process and silicide (salicide) process that are used in logic process can be used in flat cell (flat cell) type mask only A method of fabricating a masked read-only memory on a read memory. Background technique [0002] As we all know, the mask read-only memory is a kind of non-volatile element, which is suitable for masking in element manufacturing such as element isolation process, metal process, or ion implantation process for the channel region (channel region) of the memory cell. film process. Taking the ion implantation process as an example, a difference in threshold voltage occurs between a memory cell that has been ion-implanted and a memory cell that has not been ion-implanted, and this difference is used to distinguish data and record necessary information . [0003] figure 1 It is a general cell arra...

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Problems solved by technology

[0028] In the conventional technology, since the protective film is formed between the gates of the memory cell array region and then the silicide process is performed, the gap filling (gapfill) process is performed in the memory cell array region with less design margin than in the surrounding region. have many difficulties

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