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Processor and compiler

A technology of processors and compilers, applied in electrical digital data processing, instruments, memory systems, etc., can solve problems such as circuit size enlargement, and achieve the effects of reduced energy consumption, high practical value, and reduced times

Active Publication Date: 2007-07-18
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this regard, there is also a problem that the circuit size becomes larger

Method used

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  • Processor and compiler
  • Processor and compiler
  • Processor and compiler

Examples

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no. 1 example

[0049] FIG. 1 is a diagram showing the instruction format of a very long instruction word executed by a VLIW processor according to a first embodiment. As shown in FIG. 1, the VLW is 47 bits long and includes a register designation field and three instruction fields.

[0050] The register designation field is a common field that designates registers used in the three instruction fields, and includes four register designation areas (one destination register dst and bit fields designating three source registers srcA-srcC). Each of the register specifying areas dst and srcA-srcC has 5 bits for specifying one register among 32 general-purpose registers (register files) included in the VLIW processor.

[0051] The three instruction fields (first-third instruction fields) are arranged into three instructions (instructions #1-#3) that can be executed in parallel. In the case of register arithmetic instructions, a 6-bit opcode and a 3-bit operand are placed in each instruction field....

no. 2 example

[0088] Next, a VLIW processor and compiler according to the second embodiment will be explained. The VLIW processor according to the second embodiment executes a VLIW of a characteristic instruction format similar to that of the first embodiment. However, the VLIW processor according to the second embodiment includes, in addition to the register file, temporary registers that temporarily hold operation results. The difference between the VLIW processor and the compiler according to the second embodiment and the first embodiment will be mainly explained below.

[0089] FIG. 6 is a diagram showing the instruction format of a VLIW processor executed by the VLIW processor according to the second embodiment. As shown in FIG. 6, the VLOW is 56 bits long and includes a register designation field and three instruction fields.

[0090] As with the first embodiment, each of the register designation areas dst and srcA-srcC included in the register designation field has 5 bits in order ...

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Abstract

A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Description

technical field [0001] The invention relates to a processor and a compiler, in particular to a Very Long Instruction Word (VLIW) processor and the like which execute multiple instructions simultaneously. Background technique [0002] Conventionally, various types of VLIW processors including a plurality of execution units and executing a plurality of instructions included in very long instruction words per clock cycle have been proposed (for example, refer to Japanese Laid-Open Patent Publication Material No.2004-005733). [0003] Fig. 15A shows an example of the instruction format of a VLIW executed by a conventional VLIW processor. A very long instruction word is shown here, and the instruction word includes three instruction fields, in which three instructions #1-#3 that can be executed in parallel are placed. In the case of register arithmetic instructions, each instruction field has an opcode indicating the type of operation and an operand indicating the subject of th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/45G06F9/30G06F9/34G06F15/00
CPCG06F9/30156G06F9/3016G06F9/30145G06F9/3822G06F9/3885G06F9/3853
Inventor 影山贵洋西田英志田中健中岛广二
Owner SOCIONEXT INC
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