Improved erase method for a dual bit memory cell

Abstract

An erase methodology of flash memory cells (10) in a multi-bit memory array with bits disposed in normal and complimentary locations. An erase verify of bits in the normal locations is performed and if a bit in the normal location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the normal bit and the complimentary bit. An erase verify of bits in the complimentary locations is performed and if a bit in the complimentary location fails and if the maximum erase pulse count has not been reached, erase pulses are applied to both the complimentary and the normal bit locations. If the bits pass the erase verify, the bits are subjected to a soft programming verify. If the bits are overerased and if the soft programming pulse count has not been reached a soft programming pulse is applied to the overerased bit.

Description

technical field [0001] The present invention generally relates to flash memory devices, and more particularly to flash memory cells having multi-bit flash memory cells. More specifically, the present invention relates to improved methods for the multi-bit erasure, erasure confirmation, and over-erasure correction. Background technique [0002] Flash memory is a rewritable electronic memory medium that can maintain stored content in it without energy loss. The lifetime of the flash memory device is designed to have 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM), which can only erase a single bit, flash memory devices can generally be erased and written to a fixed number of multi-bit blocks or sectors. Flash memory technology evolved from the chip technology of Electronically Erasable Programmable Read-Only Memory (EEPROM), which can be erased in place. Flash memory is cheaper and denser. This new field of EEPRO...

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