Semiconductor memory having a defective memory cell relieving circuit

a technology of memory cell and relieving circuit, which is applied in the field of semiconductor memory, can solve the problems of large area of the relief circuit, long access time, and defected memory cells, and achieve the effects of avoiding the characteristics of substitution information storing memory cells, no overhead, and high reliability

Inactive Publication Date: 2005-07-21
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This design minimizes area overhead and access time overhead, enhancing chip yield and reliability by allowing substitution of defective memory cells before column selection, thus avoiding the deterioration of ferroelectric capacitor characteristics and reducing the need for dedicated writing / reading circuits.

Problems solved by technology

In a process for fabricating a semiconductor memory, defective memory cells occur often, and if the defective memory cells are fount out in an inspecting step, even if only one bit is defective, the whole of the memory chip is rejected.
However, the arrangement disclosed in the above referred JP-A-09-128991 so configured to store the substitution information by action of the ferroelectric memory cells is disadvantageous in that the whole of the relief circuit needs a large area and the access time becomes long.
Therefore, the access time becomes long.
On the other hand, the memory device disclosed in the above referred JP-A-2000-215687 is also disadvantageous in the chip area and in the access time.
In addition, it has another problem in which the characteristics of the ferroelectric capacitor is deteriorated.
Namely, the area overhead attributable to the installation of the redundant circuit is very large.
Furthermore, since the substitution information storing cells are located in the same word lines as those of the main memory cells, the substitution has not yet been achieved at the moment a signal voltage read out from the memory cell has been amplified by a sense amplifier.
Comparing with the case in which the substitution is not carried out, an overhead is inevitably generated in the access time.
In addition, since the substitution information is read out in every memory access, the deterioration in characteristics of the ferroelectric capacitors is unavoidable.
Namely, there is possibility that an erroneous substitution occurs because of the deterioration in characteristics of the substitution information storing cells.

Method used

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  • Semiconductor memory having a defective memory cell relieving circuit
  • Semiconductor memory having a defective memory cell relieving circuit
  • Semiconductor memory having a defective memory cell relieving circuit

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Experimental program
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second embodiment

[0127] Referring to FIG. 6, there is shown a circuit diagram of the Y selection circuit 11A in the As seen from FIG. 6, a plurality of bit lines are simultaneously connected to a plurality of I / O lines in accordance with the Y selection signal. For only simplification of description, in FIG. 6 the sense amplifiers are omitted and the bit lines and the I / O lines are depicted as a single line in place of a pair of complementary lines. In addition, in FIG. 6, elements corresponding to those shown in FIG. 2 are given the same reference numbers.

[0128] The bit line BL0 connected to the sense amplifier SA0 is connected to the I / O line I / O−0 through a Y switch N001 and a switch N002 which are connected in series and which are formed of an nMOS transistor. The Y selection signal YA0 is connected to a gate of the Y switch N001, and a control signal CS0 is connected through an inverter I1 to a gate of the Y switch N002.

[0129] The bit line BL1 connected to the sense amplifier SA1 is connected...

third embodiment

[0137] Referring to FIG. 8, there is shown a circuit diagram of the control circuit 12A in the As shown in FIG. 8, the control circuit 12A includes volatile memory cells RMC0 to RMC63 (RMC0 to RMCj) for storing the substitution information, and a decoder (DEC) 14. The memory cell RMC0 includes two inverters INV21 and INV22 each having an input connected to an output of the other inverter so as to form a latch circuit, and transfer gate nMOS transistors N21 and N22 having a gate connected to a write control line WLC. One end of the transfer gate nMOS transistors N21 and N22 are respectively connected to a pair of complementary output lines DR0 and / DR0 of the sense amplifier connected to the substitution information storing memory cell MCRA0. The other end of the transfer gate nMOS transistors N21 and N22 are respectively connected to two connection nodes of the inverters INV21 and INV22 connected to each other in opposite direction.

[0138] The memory cell RMC0 also includes nMOS tra...

fourth embodiment

[0157] The shown fourth embodiment includes two sub-arrays “subarray0” and “subarray1”. The “subarray0” includes a memory cell array MA1 and a plurality of sense amplifiers SA0 to SAj+1. The memory cell array MA1 includes a number of memory cells MC00 to MCij, one column of redundant memory cells MC0j+1 to MCij+1, and one word line of substitution information storing memory cells MCR0 to MCRAj+1.

[0158] Furthermore, transfer gates TG00 and TG10 to TG0j+1 and TG1j+1 are inserted between the substitution information storing memory cells and the memory cells MC00 to MCij and the redundant memory cells MC0j+1 to MCij+1, and controlled by a signal ETG to be able to selectively separate the memory cells MC00 to MCij and the redundant memory cells MC0j+1 to MCij+1, from the sense amplifiers SA0 to SAj+1.

[0159] Each bit line includes a parasite capacitance depending upon the number of the memory cells connected to the bit line concerned. In FIG. 11, parasite capacitance Cbb00 and Cbb10 to C...

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Abstract

In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j+1 to MCij+1 and one word line of substitution information storing memory cells MCRA0 to MCRAj+1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing / reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS0 to CSj so as to selectively connect the columns other than a defective column to an input / output line. Thus, a chip area overhead attributable to the installation of the defective memory cell relief circuit is minimized. In addition, an address comparing circuit for a defective memory cell substitution is no longer necessary, and an access time overhead attributable to the address substitution operation does not occur.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor memory, and more specifically to a method for relieving a defective memory cell and a semiconductor memory incorporating therein a circuit for relieving a defective memory cell. [0002] In a process for fabricating a semiconductor memory, defective memory cells occur often, and if the defective memory cells are fount out in an inspecting step, even if only one bit is defective, the whole of the memory chip is rejected. Therefore, particularly, in a semiconductor memory having a large memory capacity, redundant memory cells are previously provided to relieve the defective cells. In order to relieve the defective cells, it is necessary to provide on a chip a non-volatile memory for storing information for substituting a nondefective redundant memory cell for the defective memory cell found out in a chip test time. [0003] In the prior art, in many cases, a memory of the information for substituting the n...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C29/00G11C29/04
CPCG11C11/22G11C29/848G11C29/789
InventorYAMADA, JUNICHI
OwnerNEC CORP