Grid Processing Electronic Memory
Inactive Publication Date: 2017-02-02
BRADY AARON
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- Abstract
- Description
- Claims
- Application Information
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Benefits of technology
The patent is about a new invention that allows software programs to perform a repeated sequence of steps on multiple data simultaneously. This is possible because the data has a parallel structure. The invention is divided into two major sections: one which performs operations in a memory bank itself and enables many simultaneous operations, and another which connects storage and computation units in two dimensions, allowing list-internal or cross-row operations. The invention can use a subset of computer instructions, only applicable to single-instruction multiple-data operations, which eliminates synchronization demands and overhead associated with general multiprocessing. Additionally, the invention includes a memory bank that can perform one type of operation replicated in many replicated units simultaneously, resulting in a greater range of vector operations and an asymptotic speed improvement. This invention will improve the speed of common tasks, like sorting, and can be used in hybrid processing combinations. The responsibilities for using it are delegated to the manufacturer of the hardware, the operating system, and the software authors.
Problems solved by technology
Other operations, such as sorting, searching, summing, or copying a list, have the same limitation; and in the case of sorting, each transfer might be performed many times. Therefore, serial transferring on the front-side bus is a bottleneck.
Serial processing is also a problem.
Even with data that already exist in processor-local registers, the processor can only perform one operation at a time.
Method used
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Embodiment Construction
[0035]In this application, the subset of possible operations in the examples consists of those operations in which data can travel along independent pathways, and be handled independently.
[0036]In an example of the “time-space trade-off” often encountered in software, further capabilities of the cells will result in faster speeds, but lower storage densities on a given chip. Losses of density of up to 90% or more in favor of computational capabilities could be possible, only offering 10 gigabytes of storage on a chip that would otherwise hold 100 gigabytes; as such the particular end user's purposes are relevant.
[0037]The process shown in FIG. 11 is expected to be the most widely demanded new operation, due to its ability to copy lists to arbitrary locations in constant time. The spatial requirements for it are low, but can be implemented in two ways, as shown in FIG. 12D. One implementation adds circuitry to cells, those necessary to determine whether two of the cells' respective i...
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The invention adds execution units to a conventional memory bank, and connects memory units in two dimensions in a grid. Highly enabled execution units occur in every row in the grid; individual grid units are also enabled to varying degrees with reduced execution capabilities. The multiple execution units follow a single instruction. Row-aligned or vector operations, and cross-row or vector-internal operations, can be performed simultaneously without crossing the front-side bus. Constant-time list copying and read-write array accessing, and linear- and sublinear-time sorting are possible as a result. Extended content-addressing is introduced. The running times of matrix multiplication and Gaussian elimination are improved by factors of the size of the matrix.
Description
BACKGROUND OF THE INVENTION[0001]Field of the Invention[0002]The present application relates to computer memory device, in particular, to a novel design of computer memory device that performs computational operations in units that are located within the memory bank. Like a vector processor, multiple computational operations are performed in replicated computation units and performed simultaneously.[0003]Description of Related Art[0004]Using conventional designs to add the respective items in two lists, the numbers must be transferred from memory to the processor one at a time, the operations performed one at a time, and the results transferred back one at a time. Other operations, such as sorting, searching, summing, or copying a list, have the same limitation; and in the case of sorting, each transfer might be performed many times. Therefore, serial transferring on the front-side bus is a bottleneck. Serial processing is also a problem. Even with data that already exist in process...
Claims
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Patent Timeline
Login to View More IPC IPC(8): G06F3/06G11C15/04
CPCG06F3/0629G11C15/04G06F3/0673G06F3/0604G11C15/00G06F9/3885G06F9/38G06F15/7821
InventorBRADY, AARON
OwnerBRADY AARON