Method of forming overlay mark structure

Active Publication Date: 2020-01-09
UNITED MICROELECTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0003]A method of forming an overlay mark structure is provided in the present invention. Apart of a metal layer is removed while another part of the metal layer remains for avoiding influences of the metal layer covering an overlay mark on related measurements, and another overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.
[0005]In the method of forming the overlay mark structure according to the present invention, the metal layer is partially removed only. Therefore, the first overlay mark may not be covered by the metal layer, and the second overlay mark may be formed on the remaining metal layer. The influence of the metal layer covering the first overlay mark on the related measurements may be avoided by removing the metal layer on the first overlay mark. In addition, related defects generated by the height difference cause by the metal layer may be avoided by forming the second overlay mark on the metal layer.

Problems solved by technology

However, as the semiconductor process becomes complicated, the overlay masks of different layers may influence each other during the processes, and problems about the manufacturing and the measurements of the overlay marks are generated accordingly and have to be solved.

Method used

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  • Method of forming overlay mark structure
  • Method of forming overlay mark structure
  • Method of forming overlay mark structure

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Experimental program
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first embodiment

[0009]Please refer to FIGS. 1-8. FIGS. 1-8 are schematic drawings illustrating a method of forming an overlay mark structure according to the present invention, wherein FIG. 1, FIG. 3, FIG. 5 and FIG. 7 are top-view diagrams, and FIG. 2, FIG. 4, FIG. 6, and FIG. 8 are cross-sectional diagrams. FIG. 3 is a schematic drawing in a step subsequent to FIG. 1, FIG. 5 is a schematic drawing in a step subsequent to FIG. 3, and FIG. 7 is a schematic drawing in a step subsequent to FIG. 5. FIG. 2 is a cross-sectional diagram taken along a line A-A′ in FIG. 1, FIG. 4 is a cross-sectional diagram taken along a line B-B′ in FIG. 3, FIG. 6 is a cross-sectional diagram taken along a line C-C′ in FIG. 5, and FIG. 8 is a cross-sectional diagram taken along a line D-D′ in FIG. 7. The method of forming the overlay mark structure in this embodiment may include the following steps. As shown in FIG. 1 and FIG. 2, an insulation layer 30 is formed on a substrate 10, and a first overlay mark OM1 is formed i...

second embodiment

[0018]Please refer to FIGS. 10-13, FIG. 2, FIG. 6, FIG. 8, and FIG. 9. FIGS. 10-13 are schematic drawings illustrating a method of forming an overlay mark structure according to the present invention. FIG. 11 is a schematic drawing in a step subsequent to FIG. 10, FIG. 12 is a schematic drawing in a step subsequent to FIG. 11, and FIG. 13 is a schematic drawing in a step subsequent to FIG. 12. In addition, FIG. 10 may be regarded as a schematic drawing of the manufacturing condition the main region corresponding to the manufacturing condition of FIG. 2, FIG. 11 may be regarded as a schematic drawing of the manufacturing condition the main region corresponding to the manufacturing condition of FIG. 6, FIG. 12 may be regarded as a schematic drawing of the manufacturing condition the main region corresponding to the manufacturing condition of FIG. 8, and FIG. 13 may be regarded as a schematic drawing of the manufacturing condition the main region corresponding to the manufacturing cond...

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Abstract

A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a method of forming an overlay mark structure, and more particularly, to a method of forming an overlay mark structure including two overlay marks.2. Description of the Prior Art[0002]The manufacture of integrated circuits keeps improving as the related technologies progress. Many kinds of electric circuits may be integrated and formed on a single chip. The semiconductor process for manufacturing chips may include many steps, such as a deposition process for forming a thin film, a photoresist coating process, an exposure process, and a develop process for forming a patterned photoresist, and an etching process for patterning the thin film. In the exposure process, a photomask having a pattern to be formed has to be aligned with a base layer pattern on a wafer for transferring the pattern to a specific location on the wafer. The alignment condition maybe monitored by measuring the relative posi...

Claims

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Application Information

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Patent Type & AuthorityApplications(United States)
IPC IPC(8): H01L23/544H01L27/108H01L21/027H01L21/311H01L21/3213
CPCH01L27/10808H01L27/10823H01L2223/54426H01L21/32139H01L21/0276H01L21/31144H01L23/544H01L27/10855H01L21/0274H01L22/34H10B12/31H10B12/34H10B12/0335
InventorCHEN, ZHENG-FENGLEE, SHO-SHENLIOU, EN-CHIUANHSU, HSIAO-LINCHEN, YI-TINGKUO, LU-WEI
OwnerUNITED MICROELECTRONICS CORP