Integrated circuit having embedded differential clock tree

Abstract

A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application is a divisional of U.S. patent application Ser. No. 11 / 511,647 filed Aug. 29, 2006 (now U.S. Pat. No. 7,414,430), which is a divisional of U.S. patent application Ser. No. 10 / 837,009 filed Apr. 30, 2004 (now U.S. Pat. No. 7,126,406).FIELD OF THE INVENTION[0002]The present invention relates generally to clock circuitry on an integrated circuit (IC) and more specifically, a clock network on an IC having, at least in part, a differential clock tree.BACKGROUND OF THE INVENTION[0003]In the design of a clock-distribution network, or “clock tree,” for an integrated circuit (IC) such as application specific integrated circuit (ASIC) or a Programmable Logic Device (PLD) some of the major considerations are skew, jitter, delay, duty cycle distortion and power consumption. Various clock tree geometries such as the balanced tree (e.g., the H clock tree) and grid have been used. The H clock tree, in some cases, can provide low ...

AI Technical Summary

Benefits of technology

The present invention relates to a method and system for improving clock networks in ICs. The invention includes a hybrid clock tree with small signal differential clock signals that have lower sensitivity to power noise and consume less dynamic power than full voltage signals. The clock tree backbone and primary branches have small signal differential clock signals, while the leaf nodes may have either rail-to-rail differential clock signals or single-ended clock signals. The invention also includes a columnar architecture with a balanced tree geometry and a cross bar switch for distributing the differential clock signal to multiple programmable function elements or configurable logic elements on the IC. The invention provides a low noise clock at high clock speeds and conserves power and area.

Problems solved by technology

However, small signal differential clock circuits are more costly than either rail-to-rail differential or single ended clock circuits.

And also while small signal or rail-to-rail differential signals have less noise than single ended signals, they consume more static power.

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