52results about How to "Improve monotonicity" patented technology

A programmable gain amplifier with three stages uses fine steps, has a large gain range, and is monotonic. The first stage comprises several amplifiers, each including a resistive feedback loop. The feedback loop comprises a series of resistors, with each resistor acting as a tap. Since the number of resistors in the loop is unchanging, monotonicity and stability is guaranteed when resistance is increased using successive taps. A switch system connects two taps at a time to an interpolation stage. Each of these taps corresponds to a specific resistor level, and thus a gain level. The interpolation stage uses a plurality of current sources inside a feedback amplifier to control the interpolation, in order to provide fine gain steps.

A digitally controlled analog circuit comprises a finite state machine configured for receiving a digital input word and generating at least two digital codes in a manner determined by a state of the finite state machine. The digital codes are decoded into respective sets of binary data. The sets of binary data control respective switched-circuit arrays to generate an analog output corresponding to the digital input word. To establish a monotonic function between the digital input word and the analog output during steady state operations, the finite state machine switches states when a wrap-around condition is detected for one of the digital codes. The finite state machine uses different sets of equations in different states to derive the digital codes.

To increase the accuracy and resolution of an m bit digital analog converter, n bit input values with n>m are fed to a control circuit and converted to a series of control values for the digital analog converter using dithering techniques. When the series of control values straddles a major transition where a large number of bits are switched between 1 and 0, a corrected series of control values is retrieved from a calibration table. The corrected series takes into account the glitch effects observed at the output of digital analog converter at a major transition.

The invention discloses a turbine engine performance degradation evaluation method based on a stacked-denoising auto-encoder, and belongs to the technical field of engine performance degradation evaluation. The turbine engine performance degradation evaluation method solves the problems that traditional multi-sensor data selection needs to rely on complex information evaluation criteria, extraction of degraded features in HI construction depends on a large number of signal processing techniques and expert experience, supervised training method label selection relies on manual participation, and a method is low in universality. Four denoising auto-encoders build stacked-denoising auto-encoders to extract the single node value of input data. Training set data carries out pre-training to thenetwork and uses a BP algorithm to fine-tune parameters. The extracted single node value is considered to be the health factor value at each cycle, and an HI curve of a training set is established. The test set is input to the trained stacked-denoising auto-encoder to obtain the health factor value at each cycle and construction an HI curve. The HI curves of training set and test set are subjectedto smoothing processing respectively, and the HI curves after smoothing processing are evaluated.

The invention discloses design and a method of domain layout of a 14-bit integrated circuit DAC (Digital to Analog Converter) current source array. In the design of the domain layout of the 14-bit integrated circuit DAC (Digital To Analog Converter) current source array, a main array formed by orderly arranging a plurality of current source is comprised; the main array is divided into four main quadrants by a vertical centerline and a horizontal centerline; the current source arrays of the four main quadrants are arranged in a star-like symmetrical manner based on a center; each main quadrant is divided into four auxiliary quadrants by a vertical centerline and a horizontal centerline, and four auxiliary quadrants are arranged in a star-like symmetrical manner based on a center. Specifically, a two-layer tree-like structure is adopted, bidimentional two-step symmetrical layout is achieved, layers are relatively independent, and quadrants are relatively independent; when number input codes are increased from full 0 to full 1 and the current sources are sequentially opened, the structure can well eliminate gradient error, symmetry error and immediate technology error and has good heat-resistant gradient effect. The design has the characteristics of good monotonicity, offset error, differential and integral linearity, spurious-free dynamic range and signal to noise ratio.

The present invention provides a wireless positioning method and system, wherein the method includes: 1) when a terminal exchanges data with a wireless base station, the terminal or the wireless base station collects the actual data receiving rate of the data exchange; 2) ) executing a positioning algorithm according to the received data reception rate. Based on the solution of the present invention, there is no need to specially set up hardware devices such as GPS, and it is not necessary to deploy a large number of dedicated hardware for wireless positioning in the environment. The present invention realizes the positioning based on the data receiving rate, does not need to communicate separately for the positioning, and the data receiving rate can match with any existing wireless positioning algorithm, and can obtain a better effect than using signal strength in certain environmental conditions .

The invention provides a 10-bit high-precision digital-to-analog converter (DAC) current source array and a layout method thereof. Firstly a mirror image to be rotated is generated for replacing a 16*16 sub-array Z to be converted, and the 16*16 sub-arrays are respectively obtained by multiple times of conversion and then are further composed into a final array. According to the layout method of the invention, matching of high and low current sources in the DAC current source array can be improved, integral non-linearity (INL) and differential non-linearity (DNL) characteristics of the DAC can be reduced, and a chip area is further reduced, and the space is saved; a current mirror can copy the current more accurately; and furthermore, a stray capacitance value can also be reduced, and surges generated during conversion between an MSB and an LSB can be effectively reduced. The layout of the same center of gravity adopted by the invention can be effectively improved, the influence of a ladder degree error can be counteracted, and mismatching of the current source array caused by systematic errors and random errors can be reduced while high conversion precision and high speed are ensured, so that the DAC circuit has better performance.