Dynamic self-management buffer zone

Abstract

The present invention includes control module and cache module, wherein said cache module divided into plurality of BANK spaces; control module used for receiving outer read-write signal, controlling data writing / reading out cache module every BANK, and configuring inner BANK of cache module. Said control module also includes writing interface module, interface module, parameter configuring module, wherein writing interface module used for receiving outer write data signal and controlling data writing cache module BANK; read interface module used for receiving outer read data signal, controlling data reading out cache module BANK; parameter configuring module used for transferring configuration parameter to cache module to proceed configuring and transferring configuration parameter to writing interface module and read interface module. The present invention can simplify outside managing to buffer zone, and to make the external interface not concerning buffer zone inner BANK structure.

Description

technical field [0001] The invention relates to the technical field of buffers, in particular to a dynamic self-management buffering device. Background technique [0002] In hardware design, programmable logic devices (FPGA) are often used to complete various algorithm processing, complex interface timing conversion, and so on. However, inside the FPGA, when data is transmitted between different functional sub-modules (or logic units), cross-clock domain problems may occur, resulting in data transmission failure. For example, the logic interface module inside the FPGA is inconsistent with the processing clock of the internal module, which will cause data to fail to be transmitted normally between the two logic units. [0003] At present, buffer isolation is usually used to solve the problem of crossing clock domains, and the buffer can be implemented by FIFO or DPRAM. Among them, FIFO has the address self-increment function, so there is no need to provide an address line e...

AI Technical Summary

Problems solved by technology

[0008] 2. Waste of logical resources: The buffer is generally implemented by an embedded storage block (ESB) inside the logic. The size of each ESB is fixed. At least one ESB is required to construct a physical bank. Even if all ESB resources are not used, one bank occupies one ESB. , so that the actual utilization of the ESB is low

[0009] 3. Poor scalability: If you want to expand the number of BANKs, the management complexity will be greatly increased: As mentioned earlier, this kind of buffer requires each BANK to correspond to a physical ESB entity, so there will be independent control buses, data Bus, so that each additional BANK will introduce an additional set of buses, which will lead to more complex buffer management and further waste of logic resources

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