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Method of manufacturing a semiconductor device

A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as increased interference capacitance and reduced device reading speed

Inactive Publication Date: 2008-03-12
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In addition, if the distance between the gates is reduced, the interference capacitance between the gates will increase, thereby reducing the read speed of the device

Method used

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  • Method of manufacturing a semiconductor device
  • Method of manufacturing a semiconductor device
  • Method of manufacturing a semiconductor device

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Embodiment Construction

[0010] Specific embodiments according to the present invention will be described with reference to the drawings.

[0011] 1A to 1G are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0012] Referring to FIG. 1A , wires such as a plurality of gate structures 114 are formed at predetermined intervals over a semiconductor substrate 100 . A tunnel oxide layer 102 is formed on the substrate 100 . A first polysilicon layer 104 for the floating gate, a dielectric layer 106, a second polysilicon layer 108 for the control gate, a tungsten silicide layer 110 and a hard mask are formed on the tunnel oxide layer 102 layer 112, which is then etched to form gate structures 114.

[0013] Referring to FIG. 1B , an ion implantation process is performed using the gate structure 114 as a mask to form source and drain junctions (not shown) within the semiconductor substrate 100 . A sacrificial insulati...

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Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor substrate with gate structures. A sacrificial insulating layer is formed between the gate structures at a height lower than that of the gate structures such that a portion of each gate structure is exposed above the sacrificial insulating layer. Spacers are formed on sidewalls of the exposed portions of the gate structures. A portion of the sacrificial insulating layer between the spacers is exposed. The sacrificial insulating layer is removed, thereby forming spaces below the spacers. An insulating layer is formed to fill the spaces between the spacers such that air pockets are formed between the gate structures and below the spacers.

Description

technical field [0001] The present invention relates to a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device capable of reducing interference capacitance between gates. Background technique [0002] In the manufacturing method of NAND flash memory, with the improvement of device integration, the space for forming a unit active region and a unit field effect region is reduced. Since the dielectric layer (including the floating gate and the control gate, etc.) is formed in a narrow active space, the distance between the gates is reduced. Interfering capacitors accordingly become a problem. [0003] C=ε×A / d (where ε represents the dielectric constant, A represents the area, and d represents the distance) is a formula for calculating the interference capacitance value between conductors. It can be seen from this formula that the smaller the distance, the larger the area, the higher the dielectric constant, and the higher the inter...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/822H01L21/8247H01L21/76H01L21/764H01L21/768
CPCH01L21/823475H01L27/11521H01L21/7682H01L27/115H01L21/76885H10B69/00H10B41/30
Inventor 金守镇
Owner SK HYNIX INC