A PCIE data transmission method, system and device

Abstract

The invention discloses a method for transmitting PCIE data, which comprises the steps as follows: the vacant internal memory address is notified to an address isolation device of the wire cardboard by a goal wire cardboard CPU; the message is transmitted to the address isolation device of the goal wire cardboard by an address isolation device of the source wire cardboard by the goal wire cardboard slot-number; the message is extracted by the address isolation device of the goal wire cardboard and stored in the free internal memory address. The invention discloses a system and a device for transmitting PCIE data. The invention ensures that the address space of each wire cardboard CPU keeps mutually independent without being affected by the PCIE converter address route mode, also the invention ensures that the PCIE converter realizes forwarding by the slot-number, thus improving the packet forwarding performance of the device.

Description

technical field [0001] The present invention relates to the technical field of communication, in particular to a PCIE (PCI Express, PCI express bus) data transmission method, system and equipment. Background technique [0002] PCI (Peripheral Component Interconnect) Express is a processor system bus initiated and developed by Intel. It is a serial interconnection technology. (PCI eXtended, the successor of PCI extension), the goal is to completely replace PCI and PCI-X. With the release of the PCI Express (referred to as PCIE) specification, more and more manufacturers have begun to introduce chips based on the PCIE specification. Some manufacturers have launched switches based on PCIE, which can connect many devices in one system. Advanced communication equipment (such as routers, switches, gateways, etc.) has also become an option. [0003] In the prior art, a typical architecture of a distributed system based on a PCIE switch, such as figure 1 As shown, the PCIE switch...

AI Technical Summary

Problems solved by technology

[0012] 1. The communication protocol in the PCIE switching network is complex, which seriously affects the transmission performance between line cards: the sender needs to obtain the address of the receiver, and the address of the receiver needs to be updated to the sender

This increases the communication overhead, for example: when the receiver's address is updated to the sender, for some locked memory addresses, the receiver needs to send additional access lock overhead; and the transmission of a data packet is accompanied by PCIEMemory write The overhead of the two small packets (request address packet and get address packet) of the method, etc.

[0013] 2. The number of VC (Virtual Channel, virtual channel) in the PCIE switching network is not enough, which may easily cause HOL (Head of Line Blocking, letter head blocking) problem

If the inter-board transmission fails when performing these operations, the CPU will continue to wait, which will affect the basic operation of the CPU and cause a large transmission delay

Images