Method for implementing quadrature frequency conversion in satellite communication high speed demodulator

A technology of satellite communication and its implementation method, applied in the field of satellite communication, can solve problems such as insufficient chip capability and inability to process high-speed data signals

Inactive Publication Date: 2009-03-04
深圳市统先科技股份有限公司
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  • Application Information

AI Technical Summary

Problems solved by technology

[0005] A common numerically controlled oscillator generates a complex sequence signal and a complex sequence signal converted from an analog-to-digital converter is multiplied in a complex multiplier to realize the function of quadrature down-conversion. Due to the capability of the FPGA (programmable logic gate array) chip Insufficient, unable to handle high-speed data signals

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  • Method for implementing quadrature frequency conversion in satellite communication high speed demodulator
  • Method for implementing quadrature frequency conversion in satellite communication high speed demodulator

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Embodiment Construction

[0025] Such as Figure 1-2 Show, the realization method of the present invention, this method is realized by the analog-to-digital converter 10 in the satellite demodulator and the parallel digital control oscillator 20 in the editable logic gate array circuit, complex number multiplier 30, and its steps are:

[0026] Step 1) The analog-to-digital converter 10 converts the input sampling signal into an orthogonal digital signal, and outputs two complex sequence {a(2k)}, {a(2k+1)};

[0027] The real part sequence signal of {a(2k)}, {a(2k+1)} in the two complex number sequences is input into the complex number multiplier 30 through the I road;

[0028] The imaginary part sequence signal of {a(2k)}, {a(2k+1)} in the two complex number sequences is input into the complex number multiplier 30 through the Q road;

[0029] Step 2) Set the accumulative phase unit in the parallel numerically controlled oscillator 20 to 2n, and the sequence generated by the parallel numerically contro...

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Abstract

The invention relates to the technical field of the satellite communication, and particularly relates to a method for realizing the quadrature down-conversion of high-speed digital signals in a satellite digital demodulator. The method utilities an analog-digital converter to transform the original one-way sampled signals into two-way parallel signals; the speed is reduced to half of a sampled speed; then a complex multiplier in an FPGA is input; after that, two sine weave complex number sequence signals are generated by utilizing parallel NCOs; and each two complex number sequences are multiplied by the complex multiplier so as to realize the quadrature down-conversion. Therefore, by adopting the method to process sampled data, the efficiency of data processing can be improved, the high-speed information is processed in real time, and the defects of data processing capacity of the FPGA are made up.

Description

technical field [0001] The invention relates to the technical field of satellite communication, in particular to a method for realizing quadrature down-conversion of high-speed digital signals in a satellite digital demodulator. Background technique [0002] For satellite high-speed data transmission services, the sky data relay synchronous satellite and the terminal station on the ground constitute a real-time, broadband big data transmission chain, and its data rate ranges from 40Mb / s to hundreds of Mb / s, and even higher in the future Gb / s level. This requires a modem for broadband transmission of high-speed data. [0003] In the digital receiving system, for a digital signal with a symbol rate of up to 400Mb / s input to the receiving end, the information rate generated by sampling the symbol information at a rate of 400Msps according to at least 2 sampling points per symbol is 800Mb / s. With the current FPGA (Programmable Logic Gate Array) chip capability, its internal cl...

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Application Information

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Patent Type & AuthorityApplications(China)
IPC IPC(8): H04B7/185H04L27/00
Inventor李黎明
Owner深圳市统先科技股份有限公司