Time synchronization method, device and system of xDSL

Abstract

The invention provides an xDSL time synchronization method, device and system. The method comprises the following steps: a far-end sends a first symbol, a local end receives the first symbol, the far-end obtains the time for sending the first symbol and the time for receiving the first symbol; the local end sends a second symbol, the far-end receives the second symbol, the far-end obtains the time for sending the second symbol and the time for receiving the second symbol, when calculating the clock offset of the far-end and the local end, the far-end splits the delay of path from the local end to the far-end and the delay of path from the far-end to the local end, obtains the value of the known part, and uses the condition that the downlink delay is approximately equal to the uplink delay or the downlink delay is proportional to the uplink delay to calculate the clock offset of the far-end and the local end, and the far-end uses the offset to adjust the clock and realize synchronization. The method of the invention can accurately obtain the clock offset of the far-end and the local end and effectively realize the time synchronization of the far-end and the local end by adjusting the read clock time of the far-end and the read clock time of the local end.

Description

technical field [0001] The present invention relates to the communication field, in particular to a method, device and system for xDSL time synchronization. Background technique [0002] Due to the emergence of the third generation of mobile communication (3G) and more advanced digital mobile technology, the demand for femtocells is increasing. Femtocells have relatively high requirements for time synchronization. Generally, clock synchronization is due to the fact that terminals of network devices have clock recovery modules. It is not difficult for the network to meet the clock synchronization of femtocells. However, the realization of time synchronization needs to solve many problems. figure 1 Shown is the schematic diagram of precise time synchronization in the IEEE Pl588V2 protocol. Assume that Offset is the deviation between the slave clock and the master clock, Delay1 is the path delay from the master clock to the slave clock, and Delay2 is the path delay from the sl...

AI Technical Summary

Problems solved by technology

[0013] The xDSL receiver will detect the frame boundary and realize frame synchronization during the initialization process. In actual implementation, there may be a little error in the synchronization algorithm, and the synchronization accuracy is also limited by the sampling rate. The frame synchronization error may affect the accuracy of time synchronization. Spend

For example, the sending end uses the beginning of a certain frame as the time stamp tm1 (CO) or time stamp ts2 (CPE), when the CPE receiving end performs time marking Ts1 or when the CO receiving end performs time marking Tm2, ​​its frame synchronization is The receiving end restores it through a certain algorithm, and generally there is a certain error. D

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