Double date rate internal memory controller and control method thereof

Abstract

The invention discloses a double date rate internal memory controller and a control method thereof. The internal memory controller comprises an arbitrator, a master state machine, a refreshing management unit, a register and a power consumption management unit, wherein the master state machine feedbacks the state of a double data rate internal memory to the power consumption management; according to a note of the power consumption management, the double data rate internal memory is controlled to enter into or exit a precharging power failure state; and the power consumption management unit notices the master state machine to control the double data rate internal memory to enter into the precharging power failure state after the double data rate internal memory enters into an activated standby state and notices the master state machine to control the double data rate internal memory to exit the precharging power failure state when the arbitrator indicates that a read write command is received currently or the refreshing management unit indicates that a refreshing period is coming. By applying the controller and control method disclosed by the invention, consumption of software resource in power consumption control of the double data rate internal memory can be reduced, and a low power consumption state can rapidly exit when the read write operation is required to be carried out on the double data rate internal memory.

Description

technical field [0001] The invention relates to a double data rate (DDR, Double Data Rate) memory, in particular to a memory controller of the DDR memory and a control method thereof. Background technique [0002] DDR memory is a memory device widely used at present, and the read and write operations of DDR memory by the central processing unit (CPU, Computer Process Unit) or other hardware acceleration devices need to be realized through the memory controller. [0003] figure 1 It is a structural diagram of a memory controller in the prior art, and the memory controller includes: an arbiter, a register, a main state machine, a data first-in-first-out (Data FIFO) and a refresh management unit. [0004] The arbiter is used to arbitrate the highest priority read and write command and send it to the main state machine when multiple devices initiate read and write operations on the DDR memory at the same time; it is forwarded in the first-in-first-out data interaction between t...

AI Technical Summary

Problems solved by technology

The time required for the judgment of the above-mentioned system software is generally above the millisecond level, and in some portable systems, it is necessary to perform read and write operations on the DDR memory every fixed time, and this fixed time is usually at the millisecond level. Consumes large software resources and responds very slowly

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