Booth multiplier

A multiplier and multiplier technology, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., to achieve the effect of occupying less transistors, reducing power consumption, and simple circuits

Active Publication Date: 2015-06-03
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, there are several types of Booth encoding schemes. These encoding and decoding schemes can well realize the function of reducing partial products, but they have not been comprehensively considered from the perspective of speed, power consumption and resource occupation.

Method used

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Embodiment 1

[0031] According to the IEEE 754-1985 / 2008 standard, a binary floating-point number v can be represented by three parameters, namely the symbol S, the mantissa F and the exponent (also known as the exponent) E, and its representation is:

[0032] v=(-1) S ·2 E-bias ·1.F (1)

[0033] Among them, the sign bit S∈{0,1}, when S is 0, it means that the floating point number is non-negative, and when it is 1, it corresponds to a negative number, and its binary representation is as follows figure 1 shown. For a binary single-precision floating-point number x 1 and x 2 , their binary floating-point format is as figure 2 Shown, where bias=2 8 -1=127, v=(-1) s ·2 E-127 ×1.F; their product is shown in formula (2).

[0034] x 1 · x 2 = ( - 1 ) s 1 ...

Embodiment 2

[0059] The Booth multiplier of the present embodiment, except that the Booth decoding circuit adopts Figure 9 Except for the Booth decoding circuit shown, other features are the same as those in Embodiment 1. In this example, the decoding circuit ( Figure 9 shown) is implemented according to formula (6), and the difference from Example 1 is that formula (6) is not transformed during the code implementation process.

Embodiment 3

[0061] The Booth multiplier of this embodiment has the same characteristics as that of Embodiment 1 except that the multiplier and multiplicand judging modules are added. Described multiplier and multiplicand judging module are used for judging whether multiplier, multiplicand are zero; If at least one is zero in multiplier, multiplicand, then close Booth coding circuit, Booth decoding circuit, compressor and Carry save adder.

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Abstract

The invention discloses a Booth multiplier, which comprises a Booth coding circuit, a Booth decoding circuit, compressors and a carry save adder, wherein the Booth coding circuit is used for implementing Booth coding and coding a binary multiplying factor B to acquire signals X1, X2 and Neg; the Booth decoding circuit is used for combining the signals X1, X2 and Neg and a binary multiplicand A to generate partial product terms; the compressors are used for accumulating a plurality of partial product terms generated by the decoding circuit to acquire two accumulated values; and the carry save adder is used for implementing carry save adding operation on the two accumulated values acquired by accumulation of a plurality of partial product terms through the compressors to acquire a final product result. The operating rate is improved by adopting a hybrid Wallace-Tree structure and inserting a streamline. Compared with the prior art, the invention has the advantages that the Booth multiplier can achieve good effects on rate and area, and is low in energy consumption and accurate in calculation result at the same time.

Description

technical field [0001] The invention relates to a multiplier, in particular to a Booth multiplier. Background technique [0002] With the rapid development of computer and information technology, people have higher and higher requirements for device processing speed and performance. In various chips such as high-speed digital signal processors (DSP), microprocessors and RISC, multipliers are indispensable. There are few arithmetic and logic units, and they are often in the critical delay path. The cycle it completes a multiplication operation basically determines the main frequency of the microprocessor. Therefore, high-performance multipliers are important in modern microprocessors and high-speed digital signal processing. important components. At present, there are four main multiplier design methods, namely: parallel multiplier, shift-add multiplier, look-up table multiplier, and addition tree multiplier. Among them, the parallel multiplier is easy to implement and has ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/523
Inventor 周智恒杨开勇吴东承曾颂荣
Owner SOUTH CHINA UNIV OF TECH
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