Analog to Digital Converter
An analog-to-digital converter and conversion technology, applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., can solve the problem of insufficient suppression of stray signal components, and achieve the effect of suppressing image signal components
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no. 1 example
[0048] Figure 7 is a schematic diagram of the ADC according to the first embodiment. This example also depicts a time-interleaved ADC that performs background calibration for skew errors. There are also N=2 ADC channels 100, 200 in this example. and figure 1 similar, Figure 7 The time-interleaved ADC in has two ADC channels 100, 200 and an adder 1 that synthesizes the digital outputs D1, D2 from these channels. In addition, this ADC has an adaptive filter 15 that corrects the output of the ADC 200 of the second channel, and also has a correction circuit 20 that generates a coefficient φ14 of the adaptive filter 15 based on the digital output signal D_OUT synthesized by the adder 1 . So far, the process is the same as Figure 4 same as depicted in .
[0049] and Figure 4 In contrast, the correction circuit 20 separates the analog signal component (value a as explained above) and the image signal component (value b as explained above) caused by the skew error from the ...
no. 2 example
[0143] Figure 9 is a circuit diagram of the ADC according to the second embodiment. and Figure 7 Similar to the ADC circuit in , the circuit has two ADC channels 100, 200, an adaptive filter 15 on the second channel side and a correction circuit 20 for correcting skew errors. and Figure 7 The different components are the fact that the correction circuit 20 has separately arranged squaring circuits 7 , 8 and multipliers 7 a , 8 a for multiplying the steps. The rest of the composition and Figure 7 in the same.
[0144] In other words, in Figure 9 In the correction circuit of , y(n) in formula (12) and y in formula (17) d1 (n) The added value (output of adder 5) and its subtracted value (output of subtractor 4, 6) are squared by square circuits 7, 8, respectively, and these values are multiplied in multipliers 7a, 8a in steps, and the results are accumulated by accumulators 9, 10 respectively to determine the mean value. Then, the square root circuits 11, 12 perfor...
no. 3 example
[0147] Figure 10 is a circuit diagram of the ADC according to the third embodiment. In this ADC circuit, the correction circuit 20 has moving average filter circuits 9a, 10a instead of Figure 9 Step size multipliers 7a, 7b and accumulators 9, 10 in. The rest of the composition is the same.
[0148] The moving average filter circuit 9a, 10a is a circuit that determines an average value during a predetermined period of time. Therefore, for a value y that is output from the squaring circuit 7, 8 p1 (n), y p2 (n) to determine the average value at predetermined past sampling points. By setting an optimum number of average value sampling points, the convergence time of the least square method performed by the coefficient calculation circuit 14 can be minimized, and thus the realization and Figure 9 The result corresponding to the step size setting in .
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