Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface

A high-speed serial interface, multi-phase clock technology, applied in the direction of automatic power control, electrical components, etc., can solve the problems of wrong locking of multi-phase clock circuit, high difficulty of phase detector design, low phase detection accuracy, etc., to prevent Error lock and harmonic lock, novel idea, slow resolution effect

Inactive Publication Date: 2013-03-27
SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to provide a new type of phase detection and start-up circuit suitable for use in the multi-phase clock generation circuit of the high-speed serial interface of the forward clock. The start-up circuit is used to sol...

Method used

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  • Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface
  • Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface
  • Phase detection and starting circuit used in multiphase clock generating circuit of high-speed serial interface

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Embodiment Construction

[0019] The following will be described in detail in conjunction with the accompanying drawings of the embodiments.

[0020] refer to Figure 4 , The multi-phase clock generation circuit in the high-speed serial interface of the embodiment forward clock structure includes: a voltage-controlled delay line (VCDL), a charge pump (CP, Charge Pump), a phase detector (PD), a start-up circuit and a loop Filter (LF, Loop Filter), etc. The voltage-controlled delay line is composed of 8 delay units, and the delay of each delay unit is completely equal. Through the voltage-controlled delay line, multiple clocks CK0, CK1, CK2, CK3, CK4, and CK5 with equal phase difference can be obtained. , CK6, CK7, CK8.

[0021] figure 1 It is a block diagram of the phase detection and start-up circuit generated by the multi-phase clock, Figure 4 used in figure 1 The phase detection and start-up circuit shown. In order to illustrate the principle of the phase detection and start-up circuit, the ab...

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Abstract

A phase detection and starting circuit used in a multiphase clock generating circuit of a high-speed serial interface comprises a phase detector and a starting circuit, wherein the phase detector is provided with three input ends and two output ends, the starting circuit is connected with the input end of the phase detector, and the starting circuit comprises an AND gate, a first D trigger, a second D trigger, a third D trigger, a first CML2CMOS circuit, a second CML2CMOS circuit, a third CML2CMOS circuit, a first buffer, a second buffer and a third buffer. The circuit controls initial states of clock signals entering the phase detector when the multiphase clock generating circuit starts working, so that the wrong locking and the harmonic locking of the multiphase clock generating circuit can be effectively prevented, the phase detector adopts the current mode logic technology, the working efficiency is high, and the incoming mismatching jittering is low.

Description

technical field [0001] The invention relates to a multi-phase clock generation circuit realizing clock recovery function in a high-speed serial interface adopting a forward clock structure, especially a phase detection and start-up circuit adopted in the multi-phase clock generation circuit. Background technique [0002] In the high-speed serial interface using the forward clock, the transmitting end and the receiving end are composed of a clock channel and multiple data channels. The transmitting end sends a differential clock signal to the receiving end through the clock channel; the transmitting end sends a differential data signal to the receiving end through the data channel. The receiving end receives the differential clock signal transmitted from the clock channel, and recovers the clock signal through the clock generation circuit; the receiving end receives the differential data signal transmitted from the data channel, and recovers the data signal through the data r...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/085
Inventor 李振涛贾晨王自强郑旭强张春侯晨龙王志华
Owner SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV
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