160 results about "Current-mode logic" patented technology

A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.

A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.

A method and apparatus for creating high speed logic circuits in a CMOS environment using current steering logic cells with actively-peaked NMOS or PMOS loads and the biasing of these logic cells is disclosed. The logic cells can include, for example, buffers, AND gates, OR gates, flip-flops, and latches. The current steering cells with actively-peaked loads can provide benefits such as reduced power consumption, smaller area, and higher speed performance over conventional devices. This performance boost is preferably achieved using NMOS followers with resistively degenerated gates to create frequency peaked transfer function of current-mode logic cells. These logic cells with actively-peaked loads can advantageously be used in circuits in which relatively good power area and performance are desired for state machine logic, parallel to serial conversions, serial to parallel conversions, and the like.

A combined multiplexer and switched gain circuit (250) that selectively multiplexes differential analog signals from a primary channel (20) and a diversity channel (22) in a diversity receiver system (10) to a single output. The circuit (250) is based on a current mode logic design where a plurality of separate conduction paths (278-284) are provided between a voltage line (266) and a current source (268). An output line (264) of the circuit (250) is coupled to each conduction path (278-284) so that the differential analog signals from the primary channel (20) and the diversity channel (22) can be selectively outputted to the circuit (250). Each conduction path (278-284) includes a gain device, such as degenerative resistor, that provides signal gain or no signal gain for that conduction path (278-284). Control signals are selectively applied to switching devices (310-324) and each conduction path (278-284) so that the conduction path (278-284) can be independently selected to provide the multiplexing.

A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2x, m≧2x+y, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.

An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.

The present invention provides a low swing current mode logic circuit including: a current mode logic block having data inputs and outputs; a pre-charging circuit for pre-charging the outputs; a dynamic current source; an evaluation circuit for evaluating the logic block during an evaluation phase; and, a feedback path arranged between the outputs and the dynamic current source which is responsive to a difference between the outputs. The simplicity of generating the low swing, achieved by the feedback which may be implemented by only two transistors, is in contrast with the complexity introduced by some methods used by other logic styles for achieving low swing.