Current integrating decision feedback equalizer used in high-speed serial interface

Abstract

The invention discloses a current integrating decision feedback equalizer used in a high-speed serial interface, belonging to the field of integrated circuits. The current integrating decision feedback equalizer comprises two branches, wherein each branch is formed as follows: a signal input end orderly passes through an analogue weighting device, a CML(Current-Mode Logic) D trigger and a CML to CMOS (Complementary Metal Oxide Semiconductor) level switching circuit to be connected with a TSPC (True Single Phase Clock) D trigger; the input end of a weighting decision selecting module is respectively connected with the output ends of the two branches and the output ends of the CML to CMOS level switching circuits in the two branches, and the output end of the weighting decision selecting module is respectively connected with the feedback control ends of the analogue weighting devices in the two branches; the output end of one input clock buffer module is respectively connected with the clock control input ends of the CML D triggers and the clock control input ends of the TSPC D triggers in the two branches; and the clock signal of the input clock buffer module is an anti-phase half-speed differential clock signal. The current integrating decision feedback equalizer has the advantages of low error rate, simple structure, low power consumption, and so on.

Description

technical field [0001] The invention relates to a decision feedback equalizer, in particular to a current integral decision feedback equalizer used in a high-speed serial interface, and belongs to the field of integrated circuits. Background technique [0002] Input-output (I / O) has always played a key role in computer and industrial applications. However, as signal processing becomes more complex, I / O communication can become unreliable. In early parallel I / O buses, data alignment issues at the interface affected effective communication with external devices. And, as higher transmission speeds become more prevalent in digital designs, managing signal delays becomes difficult in terms of data flow, pin count, electromagnetic interference (EMI), cost, and backplane efficiency. etc., the serial I / O greatly demonstrates its advantages. [0003] However, with the continuous improvement of data frequency, serial I / O also has its inherent problems. In the process of high-speed ...

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Problems solved by technology

Otherwise, detected data values ​​are passed to distortion estimation and degrade performance

[0005] There are also the following challenges for the DFE technology itself: on the one hand, because the interface I / O has accounted for more than 50% of the overall power consumption of the system in today's high-speed digital communication systems, it can be adapted to high-speed, low-power DFE technology has become an inevitable trend

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