Novel decoder and decoding method

Abstract

The invention provides a novel decoder and a decoding method. The novel decoder at least comprises a DDR, a variable-length decoding engine, a data management module and a direct memory access module, wherein the DDR is used for caching a video bitstream before decoding and output data of the variable-length decoding engine; the variable-length decoding engine is used for decoding the video bitstream obtained from the DDR and outputting the decoded data into the data management module; the data management module is used for outputting the decoded data of the variable-length decoding engine to the direct memory access module and outputting the data obtained from the direct memory access module; the direct memory access module is used for outputting the decoded data, output by the data management module, of the variable-length decoding engine into the DDR and outputting the decoded data, obtained from the DDR, of the variable-length decoding engine to the data management module. According to the novel decoder, a reading channel and a writing channel are added to the direct memory access module, namely a small logic is increased, and two 416X22 single-port SRAMs and two sets of registers for caching parameters are omitted. Thus, compared with design in the prior art, the novel decoder has the advantages that the comprehensive area of a chip is saved by about 80000 square micrometers, the integral area of the chip is reduced by about 6%, and therefore cost of the corresponding chip is greatly reduced.

Description

technical field [0001] The invention relates to a data cache in a multi-format video decoder, in particular to the application of DDR-based buffer in a multi-format video decoder. Background technique [0002] Currently, video decoders are widely used in monitoring, digital broadcasting, and handheld devices, and are all-in-one, including multiple video codec standards H.264 / H.265, MPEG-2 / MPEG-4, VC- 1. The demand for AVS / AVS+ and other format decoders is becoming more and more obvious. The current video decoder generally adopts a multi-stage pipeline architecture: for example, entropy decoding (VLD)->motion vector prediction (MVG)->inverse quantization and inverse transformation (IQIT)->reconstruction (RECON)->filtering (LF) Similar to the architecture, RAM ping-pong is used for caching between pipelines. The problem caused by this is that the caching RAM will occupy a certain chip area, which will result in a waste of chip area and an increase in production co...

AI Technical Summary

Problems solved by technology

That is, the above-mentioned data buffer and parameter buffer account for 2.5% and 3.5% of the entire decoding chip area respectively, resulting in a waste of chip area and an increase in production cost

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