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A memory cell resistant to soft failures and latches and flip-flops

A storage unit, soft failure technology, applied in static memory, digital memory information, information storage, etc.

Active Publication Date: 2017-04-19
COMMUNICATION UNIVERSITY OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is how to effectively eliminate the adverse effects of memory unit soft failure on the circuit

Method used

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  • A memory cell resistant to soft failures and latches and flip-flops
  • A memory cell resistant to soft failures and latches and flip-flops
  • A memory cell resistant to soft failures and latches and flip-flops

Examples

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Embodiment Construction

[0055] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments. The following examples serve to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0056] figure 1 It is a traditional anti-soft failure circuit structure diagram; the anti-soft failure circuit includes four pull-up PMOS transistors, called the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3, and the fourth MOS transistor MP4; The sources of the four pull-up PMOS transistors are all grounded; the first MOS transistor and the second MOS transistor are connected through cross-coupling to form a cross-coupled pull-up PMOS transistor, and the gates of the third MOS transistor and the fourth MOS transistor The poles are respectively connected to the drains of the first MOS transistor and the second MOS transistor to maintain the value of the A and B nodes. The t...

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PUM

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Abstract

The invention discloses a soft failure resistant memory cell, a latch and a trigger. The soft failure resistant memory cell comprises a soft failure resistant circuit, wherein a cross coupling pull-down NMOS (N-channel metal oxide semiconductor) pipe and a pull-down maintaining NMOS pipe of the soft failure resistant circuit are both connected with NMOS pipes respectively; the soft failure resistant memory cell also comprises a phase inverter, the drain electrode of the cross coupling pull-down NMOS pipe is connected with the grid electrode of the NMOS pipe serially connected with the pull-down maintaining NMOS pipe by the phase inverter. The soft failure resistant memory cell, the latch and the trigger can effectively improve the soft failure resistant capability of the sequential circuit under the conditions of low delay and power consumption loss, and has important application value and the practical significance for the soft failure obvious increasingly.

Description

technical field [0001] The invention relates to the technical field of anti-soft failure, and more particularly relates to an anti-soft failure storage unit, a latch and a flip-flop. Background technique [0002] Soft failure is mainly caused by a large number of carriers generated by alpha rays entering Si; because Si materials or tube and shell materials contain more or less radioactive elements such as U and Th, when the nuclei of these elements fission That is, α-rays are generated; α-rays can penetrate 20-30 μm deep into Si, and can generate 10fC electron-hole pairs in every 1 μm; these carrier charges can destroy the data stored in the memory, but This damage is temporary, so it is called soft failure. [0003] The main ideas of anti-soft failure circuits in the prior art include: [0004] (1) Redundant memory cells store information such that the effect of a soft failure on one of the cells does not change the output of the circuit. For example, triple module redun...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/34
Inventor 吴梅梅王妍刘静王元中
Owner COMMUNICATION UNIVERSITY OF CHINA