An improved mash structure sigma-delta modulator

A modulator and an improved technology, applied in the direction of code conversion, electrical components, analog conversion, etc., can solve the problems of output spectrum spurious, limited length of SP-MASH structure sequence, etc., and achieve the effect of simple structure of the modulator

Active Publication Date: 2020-05-08
FUZHOU UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that the PM-MASH structure and the SP-MASH structure sequence length are limited, resulting in spurious output spectrum, the present invention provides an improved MASH structure Sigma-Delta modulator, which has a simple structure, and the output sequence is consistent with the input value and Initial conditions are irrelevant

Method used

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  • An improved mash structure sigma-delta modulator
  • An improved mash structure sigma-delta modulator
  • An improved mash structure sigma-delta modulator

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Embodiment Construction

[0029] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0030] Such as figure 1 As shown, an improved MASH structure Sigma-Delta modulator of the present embodiment includes a first modulator unit module and a cascaded module group composed of modulator cascaded unit modules cascaded sequentially at more than one level; The first modulator unit module is cascaded with the cascade module group; the first modulator unit module is composed of a first modulator and a first adder; the output terminal of the first modulator is connected with the cascade module The input end of the first adder is connected to the input end of the first adder and the output end of the first modulator and the output end of the cascade module group, and the input end of the first modulator unit module is the first The input end of the modulator, the output end of the first modulator unit module is the output end of the firs...

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Abstract

The invention relates to an improved MASH structure Sigma-Delta modulator comprising a first modulator unit module and a cascaded module set consisting of more than one stage of modulator cascade unit modules cascaded in sequence, wherein the first modulator unit module is cascaded with the cascade module set; the first modulator unit module is composed of a first modulator and a first adder; and the output end of the first modulator is connected with the input end of the cascade module set, the input end of the first adder is electrically connected with the output end of the first modulator and the output end of the cascade module set, the input end of the first modulator unit module is the input end of the first modulator, and the output end of the first modulator unit module is the output end of the first adder.The Sigma-Delta modulator provided by the invention has the beneficial effects of simple structure and more convenience in operation; the length of a sequence output by the Sigma-Delta modulator provided by the invention is independent of an input value and an initial condition.

Description

technical field [0001] The invention relates to the technical field of fractional frequency division frequency, in particular to an improved Sigma-Delta modulator with MASH structure. Background technique [0002] Since the birth of Sigma-Delta modulation technology in the 1960s, after several years of development, it has become one of the mainstream technologies for realizing high-performance analog-to-digital conversion interface circuits in VLSI systems. The Sigma-Delta data converter based on the Sigma-Delta modulation technology, combined with the application of oversampling technology and noise shaping technology, can push the quantization noise to the high frequency end, thereby significantly improving the signal-to-noise ratio of the data converter. In short, a Sigma-Delta modulator is used to convert a continuous-time, continuous-amplitude input signal into a discrete-time, discrete-amplitude output sequence. [0003] With the rapid development of wireless communic...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M3/00
CPCH03M3/402
Inventor 施隆照黄燕华阴亚东
Owner FUZHOU UNIV
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