Digital low-dropout voltage stabilizer

Abstract

The invention provides a digital low-dropout voltage stabilizer. The digital low-dropout voltage stabilizer comprises a power adjusting transistor, a first sampling resistor, a second sampling resistor and a pulse width modulation generation circuit, wherein a source electrode of the power adjusting transistor is connected to power voltage; a drain electrode of the power adjusting transistor is used as an output end; the power adjusting transistor is grounded through the first sampling resistor and the second sampling resistor which are connected in series; a grid electrode of the power adjusting transistor receives control signals produced by the pulse width modulation generation circuit to implement switch-on and switch-off of the power adjusting transistor; the pulse width modulation generation circuit is connected to reference voltage to realize voltage input; and the pulse width modulation generation circuit is connected to a part between the first sampling resistor and the second sampling resistor and is used for receiving sampling signals fed back by the first sampling resistor and the second sampling resistor. Compared with the correlation technique, the digital low-dropout voltage stabilizer is simple in structure, small in output voltage ripple wave, stable in performance and low in cost.

Description

【Technical field】 [0001] The invention relates to the field of electronic circuits, in particular to a digital low-dropout regulator. 【Background technique】 [0002] In the application of integrated circuits, in order to meet the needs of various application scenarios, different levels are often required. For example, in System on Chip (SOC), various power supply voltages are required. Low dropout regulators (low dropout regulators, LDOs) implement various power supply voltage needs in SOCs. [0003] The LDO mainly has two types: one is realized by pure analog, the advantage of this type of structure is that the power supply ripple is relatively small, but the loop compensation is relatively complicated, so that the chip area is relatively large and the cost is relatively high; the other is Classes are implemented in a digital way, with small area, low cost, and a relatively short development cycle for the conversion process, which has become the mainstream of development. ...

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Problems solved by technology

[0003] The LDO mainly has two types: one is realized by pure analog, the advantage of this type of structure is that the power supply ripple is relatively small, but the loop compensation is relatively complicated, so that the chip area is relatively large and the cost is relatively high; the other is Class is implemented in a digital way, with small area, low cost, relatively short development cycle of conversion process, and has become the mainstream of development

[0004] However, an additional clock generation circuit is required in the digital low-dropout voltage regulator of the related art, and the voltage ripple size of the LDO output is related to the clock period. In order to meet the requirements of the power supply ripple under different load conditions, a complex control circuit is required to implementation, increasing the cost of the LDO

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