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A kind of preparation technology of welding pad structure

A preparation process and pad technology, applied in the field of semiconductor manufacturing, can solve the problems of accumulating charges in the PI layer, prolonging the process cycle, increasing the cost of the back-end process, etc., so as to reduce the production cost and shorten the preparation cycle.

Active Publication Date: 2019-12-06
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0014] However, in the preparation process of the above pad structure, there are the following problems: first, the deposition of the passivation layer and the PI layer will greatly increase the cost of the back-end process, and will greatly prolong the manufacturing cycle of the back-end process; Second, it is precisely because of the existence of the passivation layer and the light-absorbing layer (such as TiN) that it is necessary to etch after the PI layer is baked and solidified to expose the surface of the pad metal layer 3, and this aspect will undoubtedly prolong the process. The entire process cycle, on the other hand, the plasma dry etching (Dry Etch) of the passivation layer can also easily lead to the accumulation of charges in the PI layer, which in turn leads to the need for subsequent additional alloying treatments to eliminate these unnecessary charges to avoid degradation. The performance of semiconductor products

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  • A kind of preparation technology of welding pad structure
  • A kind of preparation technology of welding pad structure
  • A kind of preparation technology of welding pad structure

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Embodiment Construction

[0042] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as ch...

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Abstract

The invention provides a preparation process of a welding pad structure. An organic polymer with high dielectric constant and excellent channel filling performance is adopted to replace a silicon oxide passivating layer in the prior art to complete channel filling and covering after a welding pad metal layer is etched, so as to protect the welding pad metal layer from being damaged by a subsequentprocess; deposition of an oxide passivation layer is omitted, and a titanium nitride light absorption layer on the top layer is removed after the welding pad metal layer is etched; in addition, in the subsequent welding pad metal layer surface exposing step, plasma dry etching is not needed to remove the oxide and the top layer titanium nitride; and therefore, subsequent alloying treatment is notneeded to eliminate PI layer charge accumulation caused by the plasma dry etching, so that the post-section preparation period is shortened, and production cost is greatly lowered.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a process method of a back-end process, in particular to a process for preparing a pad structure. Background technique [0002] With the rapid development of microelectronics technology, the size of CMOS (Complementary Metal Oxide Semiconductor) devices is also decreasing day by day. The current mainstream semiconductor process size has reached the order of 90nm and 65nm, and correspondingly, new requirements are constantly being put forward for the process technology. [0003] Among them, in the back-end process (Back-End-Of-Line, BEOL) of the semiconductor manufacturing process, after the top metal (Top Metal) wiring layer is fabricated, an inter-metal dielectric layer needs to be fabricated on the top metal wiring layer And the metal pad, the inter-metal dielectric layer is usually silicon oxide, and the metal pad is usually an aluminum pad (Al PAD), the metal pad b...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60
CPCH01L24/11H01L2224/11444H01L2224/1161H01L2224/11848
Inventor 胡小龙高晶毛晓明叶伟
Owner YANGTZE MEMORY TECH CO LTD
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